Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_nb_in_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.43 99.17 95.65 83.33 94.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe 94.43 99.17 95.65 83.33 94.00 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.43 99.17 95.65 83.33 94.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.43 99.17 95.65 83.33 94.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
TOTAL12011999.17
CONT_ASSIGN11811100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
ALWAYS199494897.96
ALWAYS30333100.00
ALWAYS31133100.00
ALWAYS31988100.00
ALWAYS33266100.00
ALWAYS34499100.00
ALWAYS36177100.00
CONT_ASSIGN37511100.00
ALWAYS37855100.00
ALWAYS38855100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN41211100.00
ALWAYS42233100.00
CONT_ASSIGN42511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
132 1 1
133 1 1
135 1 1
141 1 1
145 1 1
149 1 1
154 1 1
160 1 1
161 1 1
168 1 1
169 1 1
172 1 1
178 1 1
180 1 1
186 1 1
188 1 1
189 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
207 1 1
208 1 1
211 1 1
216 1 1
218 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
232 1 1
233 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 0 1
247 1 1
251 1 1
256 1 1
257 1 1
MISSING_ELSE
265 1 1
267 1 1
268 1 1
269 1 1
270 1 1
271 1 1
273 1 1
278 1 1
279 1 1
280 1 1
281 1 1
283 1 1
284 1 1
285 1 1
287 1 1
288 1 1
290 1 1
303 1 1
304 1 1
306 1 1
311 1 1
312 1 1
314 1 1
319 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
326 1 1
327 1 1
332 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
MISSING_ELSE
344 1 1
345 1 1
346 1 1
347 1 1
349 1 1
350 1 1
351 1 1
352 1 1
354 1 1
361 1 1
363 1 1
364 1 1
365 1 1
366 1 1
MISSING_ELSE
369 1 1
370 1 1
MISSING_ELSE
375 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
388 1 1
389 1 1
391 1 1
392 1 1
394 1 1
405 1 1
412 1 1
422 2 2
423 1 1
425 1 1


Cond Coverage for Module : usb_fs_nb_in_pe
TotalCoveredPercent
Conditions11511095.65
Logical11511095.65
Non-Logical00
Event00

 LINE       135
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T3,T27
1011CoveredT56,T44,T68
1101CoveredT1,T3,T27
1110CoveredT2,T3,T28
1111CoveredT1,T3,T27

 LINE       135
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT2,T3,T22
10CoveredT1,T3,T27
11CoveredT3,T23,T4

 LINE       141
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T22

 LINE       145
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       145
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       149
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T3,T27
101CoveredT56,T68,T58
110CoveredT1,T2,T3
111CoveredT1,T3,T27

 LINE       149
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       154
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidNak))
             ------1-----    -------2------    ----------3----------
-1--2--3-StatusTests
011CoveredT20,T22,T38
101CoveredT56,T68,T58
110CoveredT1,T2,T3
111CoveredT20,T38,T91

 LINE       154
 SUB-EXPRESSION (rx_pid == UsbPidNak)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       161
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT3,T65,T56
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT83,T92,T93
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
             -----1----   -----------------2-----------------
-1--2-StatusTests
01CoveredT65,T79,T82
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       180
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------
-1--2-StatusTests
01CoveredT1,T3,T27
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       186
 EXPRESSION (((in_xact_state == StIdle) || (in_xact_state == StWaitAck)) && in_token_received)
             -----------------------------1-----------------------------    --------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T27

 LINE       186
 SUB-EXPRESSION ((in_xact_state == StIdle) || (in_xact_state == StWaitAck))
                 ------------1------------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T3,T27
01CoveredT1,T3,T27
10CoveredT1,T2,T3

 LINE       186
 SUB-EXPRESSION (in_xact_state == StIdle)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       186
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       188
 EXPRESSION (in_starting & ep_active)
             -----1-----   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T65,T82
11CoveredT1,T3,T27

 LINE       207
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------
-1--2-StatusTests
01CoveredT3,T65,T82
10CoveredT1,T2,T3
11CoveredT1,T3,T27

 LINE       239
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------
-1--2-StatusTests
00CoveredT1,T3,T27
01CoveredT1,T27,T16
10CoveredT1,T3,T27

 LINE       239
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------
-1--2-StatusTests
01CoveredT1,T3,T27
10CoveredT1,T27,T16
11CoveredT1,T27,T16

 LINE       269
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT1,T3,T27
1CoveredT20,T73,T94

 LINE       283
 EXPRESSION (ep_active ? StRcvdIn : StIdle)
             ----1----
-1-StatusTests
0Not Covered
1CoveredT95,T96,T97

 LINE       322
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT20,T38,T4

 LINE       335
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------
-1-StatusTests
0CoveredT1,T3,T27
1CoveredT1,T2,T3

 LINE       337
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       337
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T3,T27
1CoveredT1,T3,T27

 LINE       363
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T77,T65
11CoveredT3,T23,T4

 LINE       365
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----
-1--2-StatusTests
01CoveredT98
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       365
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       391
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T27
11CoveredT1,T3,T27

 LINE       391
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       405
 EXPRESSION (((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))) & rollback_in_xact)
             -----------------------------------------------------1----------------------------------------------------   --------2-------
-1--2-StatusTests
01CoveredT20,T38,T91
10CoveredT1,T3,T27
11CoveredT20,T22,T38

 LINE       405
 SUB-EXPRESSION ((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received))))
                 ----------------1----------------    ---------------------------------2---------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T27
10CoveredT1,T3,T27

 LINE       405
 SUB-EXPRESSION (in_xact_state == StWaitAckStart)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       405
 SUB-EXPRESSION ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))
                 --------------1-------------    ------2-----    --------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T27
110CoveredT20,T38,T91
111CoveredT1,T3,T27

 LINE       405
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       412
 EXPRESSION ((in_xact_state == StWaitAck) && nak_received)
             --------------1-------------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T27
11CoveredT20,T38,T91

 LINE       412
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T27

 LINE       423
 EXPRESSION (in_starting & (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0))
             -----1-----   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T27
11CoveredT1,T4,T5

 LINE       423
 SUB-EXPRESSION (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0)
                 ----1---
-1-StatusTests
0CoveredT3,T65,T56
1CoveredT1,T2,T3

FSM Coverage for Module : usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 12 10 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: in_xact_state
statesLine No.CoveredTests
StIdle 323 Covered T1,T2,T3
StRcvdIn 208 Covered T1,T3,T27
StSendData 223 Covered T1,T3,T27
StWaitAck 268 Covered T1,T3,T27
StWaitAckStart 245 Covered T1,T3,T27
StWaitTxEnd 247 Covered T1,T3,T27


transitionsLine No.CoveredTests
StIdle->StRcvdIn 208 Covered T1,T3,T27
StRcvdIn->StIdle 323 Covered T1,T3,T4
StRcvdIn->StSendData 223 Covered T1,T3,T27
StSendData->StIdle 323 Covered T99,T100,T79
StSendData->StWaitAckStart 245 Not Covered
StSendData->StWaitTxEnd 247 Covered T1,T3,T27
StWaitAck->StIdle 323 Covered T1,T3,T27
StWaitAck->StRcvdIn 283 Covered T95,T96,T97
StWaitAckStart->StIdle 323 Covered T20,T73,T94
StWaitAckStart->StWaitAck 268 Covered T1,T3,T27
StWaitTxEnd->StIdle 323 Not Covered
StWaitTxEnd->StWaitAckStart 257 Covered T1,T3,T27



Branch Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
Branches 50 47 94.00
TERNARY 161 2 2 100.00
CASE 205 21 18 85.71
IF 303 2 2 100.00
IF 311 2 2 100.00
IF 319 3 3 100.00
IF 332 4 4 100.00
IF 344 3 3 100.00
IF 363 3 3 100.00
IF 369 2 2 100.00
IF 378 3 3 100.00
IF 388 3 3 100.00
IF 422 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 161 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T65,T56


LineNo. Expression -1-: 205 case (in_xact_state) -2-: 207 if ((ep_active && in_token_received)) -3-: 218 if (in_ep_iso_i[in_ep_index]) -4-: 225 if (in_ep_stall_i[in_ep_index]) -5-: 228 if (has_data_q) -6-: 239 if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i))) -7-: 240 if (in_ep_iso_i[in_ep_index]) -8-: 244 if (tx_pkt_end_i) -9-: 256 if (tx_pkt_end_i) -10-: 267 if (rx_pkt_start_i) -11-: 269 if ((timeout_cntdown_q == '0)) -12-: 278 if (ack_received) -13-: 281 if (in_token_received) -14-: 283 (ep_active) ? -15-: 285 if (rx_pkt_end_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T3,T27
StIdle 0 - - - - - - - - - - - - - Covered T1,T2,T3
StRcvdIn - 1 - - - - - - - - - - - - Covered T99,T100,T79
StRcvdIn - 0 1 - - - - - - - - - - - Covered T3,T65,T101
StRcvdIn - 0 0 1 - - - - - - - - - - Covered T1,T3,T27
StRcvdIn - 0 0 0 - - - - - - - - - - Covered T1,T4,T5
StSendData - - - - 1 1 - - - - - - - - Covered T99,T100,T79
StSendData - - - - 1 0 1 - - - - - - - Not Covered
StSendData - - - - 1 0 0 - - - - - - - Covered T1,T3,T27
StSendData - - - - 0 - - - - - - - - - Covered T1,T3,T27
StWaitTxEnd - - - - - - - 1 - - - - - - Covered T1,T3,T27
StWaitTxEnd - - - - - - - 0 - - - - - - Covered T1,T3,T27
StWaitAckStart - - - - - - - - 1 - - - - - Covered T1,T3,T27
StWaitAckStart - - - - - - - - 0 1 - - - - Covered T20,T73,T94
StWaitAckStart - - - - - - - - 0 0 - - - - Covered T1,T3,T27
StWaitAck - - - - - - - - - - 1 - - - Covered T1,T3,T27
StWaitAck - - - - - - - - - - 0 1 1 - Covered T95,T96,T97
StWaitAck - - - - - - - - - - 0 1 0 - Not Covered
StWaitAck - - - - - - - - - - 0 0 - 1 Covered T20,T22,T38
StWaitAck - - - - - - - - - - 0 0 - 0 Covered T1,T3,T27
default - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 303 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 311 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 319 if ((!rst_ni)) -2-: 322 if ((link_reset_i || (!link_active_i)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 332 if ((!rst_ni)) -2-: 335 if ((in_xact_state == StIdle)) -3-: 337 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T27
0 0 0 Covered T1,T3,T27


LineNo. Expression -1-: 344 if ((!rst_ni)) -2-: 349 if (in_token_received)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((setup_token_received && ep_active)) -2-: 365 if (((in_xact_state == StWaitAck) && ack_received))

Branches:
-1--2-StatusTests
1 - Covered T3,T23,T4
0 1 Covered T1,T3,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (in_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T20,T38,T73
0 Covered T1,T2,T3


LineNo. Expression -1-: 378 if ((!rst_ni)) -2-: 380 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 388 if ((!rst_ni)) -2-: 391 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T3,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 422 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_in_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InXactStateValid_A 505334164 505126465 0 0


InXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%