Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15218214	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15985749	1		T1	94		T2	236		T3	52

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	30583826	1		T1	72		T2	148		T3	35
values[0x0]	309847	1		T1	31		T2	328		T3	18
values[0x1]	310290	1		T1	27		T2	316		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12130077	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19073886	1		T1	99		T2	307		T3	54

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	82950	1		T1	2		T36	3		T7	2
valid_sources[0x01]	84463	1		T1	3		T2	1		T3	1
valid_sources[0x02]	84804	1		T2	8		T3	1		T7	1
valid_sources[0x03]	82473	1		T2	4		T3	1		T19	364
valid_sources[0x04]	141618	1		T2	5		T18	3		T19	319
valid_sources[0x05]	86209	1		T1	2		T2	11		T7	2
valid_sources[0x06]	138390	1		T2	4		T33	1		T7	1
valid_sources[0x07]	314888	1		T2	1		T39	2		T31	1
valid_sources[0x08]	105628	1		T19	353		T105	2		T104	154
valid_sources[0x09]	100735	1		T3	1		T31	1		T7	1
valid_sources[0x0a]	87101	1		T2	6		T19	321		T21	1
valid_sources[0x0b]	84296	1		T2	2		T3	1		T7	2
valid_sources[0x0c]	122779	1		T7	1		T19	342		T104	133
valid_sources[0x0d]	221237	1		T31	1		T19	352		T104	138
valid_sources[0x0e]	84249	1		T37	1		T7	3		T19	359
valid_sources[0x0f]	85377	1		T2	2		T3	2		T19	315
valid_sources[0x10]	255376	1		T1	2		T7	1		T19	372
valid_sources[0x11]	89622	1		T1	1		T2	1		T3	1
valid_sources[0x12]	84066	1		T7	2		T19	378		T308	1
valid_sources[0x13]	83780	1		T2	3		T31	1		T37	1
valid_sources[0x14]	138582	1		T1	2		T2	5		T37	1
valid_sources[0x15]	109005	1		T2	5		T7	1		T19	371
valid_sources[0x16]	210335	1		T2	6		T7	2		T19	345
valid_sources[0x17]	260881	1		T19	379		T104	130		T141	1
valid_sources[0x18]	84881	1		T2	1		T7	1		T19	370
valid_sources[0x19]	84489	1		T3	2		T7	2		T19	354
valid_sources[0x1a]	143542	1		T3	1		T7	1		T19	344
valid_sources[0x1b]	169862	1		T2	3		T19	346		T105	3
valid_sources[0x1c]	84586	1		T1	2		T29	1		T7	1
valid_sources[0x1d]	84489	1		T2	3		T32	1		T7	2
valid_sources[0x1e]	232552	1		T2	2		T3	1		T19	387
valid_sources[0x1f]	83473	1		T2	5		T7	3		T19	340
valid_sources[0x20]	83396	1		T2	4		T3	1		T34	13
valid_sources[0x21]	132037	1		T2	4		T67	1		T19	329
valid_sources[0x22]	199054	1		T2	5		T7	1		T19	380
valid_sources[0x23]	86055	1		T19	376		T104	125		T142	2
valid_sources[0x24]	85400	1		T2	3		T3	1		T30	1
valid_sources[0x25]	107215	1		T32	1		T19	317		T109	1
valid_sources[0x26]	84038	1		T1	1		T31	1		T7	1
valid_sources[0x27]	84457	1		T1	1		T2	2		T37	1
valid_sources[0x28]	83004	1		T2	2		T33	1		T74	10
valid_sources[0x29]	136629	1		T2	2		T7	1		T19	351
valid_sources[0x2a]	83818	1		T2	3		T7	1		T19	390
valid_sources[0x2b]	85569	1		T31	1		T7	1		T19	353
valid_sources[0x2c]	83413	1		T2	5		T7	1		T19	354
valid_sources[0x2d]	177312	1		T1	1		T2	8		T33	1
valid_sources[0x2e]	85534	1		T1	5		T39	1		T19	310
valid_sources[0x2f]	287948	1		T2	5		T19	386		T104	133
valid_sources[0x30]	85160	1		T2	1		T7	2		T19	363
valid_sources[0x31]	83584	1		T1	1		T2	1		T7	1
valid_sources[0x32]	83588	1		T2	1		T19	358		T86	1
valid_sources[0x33]	83332	1		T2	2		T19	358		T104	135
valid_sources[0x34]	166612	1		T1	1		T2	1		T3	1
valid_sources[0x35]	84592	1		T2	1		T19	355		T228	2
valid_sources[0x36]	141343	1		T2	5		T38	1		T19	377
valid_sources[0x37]	157500	1		T2	6		T4	41772		T36	1
valid_sources[0x38]	83457	1		T2	6		T37	1		T7	1
valid_sources[0x39]	339589	1		T2	4		T31	2		T19	329
valid_sources[0x3a]	296230	1		T2	2		T33	1		T7	2
valid_sources[0x3b]	199534	1		T2	4		T19	361		T228	2
valid_sources[0x3c]	84335	1		T1	4		T2	2		T7	1
valid_sources[0x3d]	215177	1		T2	1		T19	346		T228	8
valid_sources[0x3e]	85386	1		T1	4		T2	2		T7	1
valid_sources[0x3f]	85510	1		T2	6		T38	1		T7	1
valid_sources[0x40]	190712	1		T2	1		T3	4		T7	2
valid_sources[0x41]	83902	1		T2	4		T7	1		T19	353
valid_sources[0x42]	163932	1		T2	6		T31	1		T19	342
valid_sources[0x43]	84083	1		T2	5		T28	11		T19	344
valid_sources[0x44]	84169	1		T7	1		T19	386		T104	136
valid_sources[0x45]	84512	1		T2	1		T3	1		T37	1
valid_sources[0x46]	127378	1		T1	1		T2	1		T36	2
valid_sources[0x47]	83939	1		T2	2		T7	1		T19	317
valid_sources[0x48]	84324	1		T2	4		T19	352		T228	4
valid_sources[0x49]	133511	1		T2	1		T7	2		T19	349
valid_sources[0x4a]	87108	1		T2	1		T31	1		T7	1
valid_sources[0x4b]	113347	1		T1	1		T2	1		T3	1
valid_sources[0x4c]	83639	1		T2	11		T31	1		T19	354
valid_sources[0x4d]	261045	1		T2	9		T19	361		T228	2
valid_sources[0x4e]	166362	1		T2	3		T7	1		T19	350
valid_sources[0x4f]	85020	1		T2	3		T31	1		T32	1
valid_sources[0x50]	83328	1		T2	2		T7	1		T19	363
valid_sources[0x51]	187746	1		T2	5		T19	349		T86	1
valid_sources[0x52]	82331	1		T1	1		T2	1		T3	1
valid_sources[0x53]	85041	1		T1	3		T3	1		T19	331
valid_sources[0x54]	84219	1		T2	1		T37	3		T7	1
valid_sources[0x55]	102273	1		T2	1		T7	1		T19	343
valid_sources[0x56]	121998	1		T1	1		T2	2		T33	1
valid_sources[0x57]	110349	1		T2	1		T31	1		T32	1
valid_sources[0x58]	85915	1		T33	1		T19	330		T308	1
valid_sources[0x59]	84880	1		T1	2		T2	2		T37	1
valid_sources[0x5a]	91289	1		T7	1		T19	360		T228	1
valid_sources[0x5b]	83725	1		T2	3		T38	1		T7	1
valid_sources[0x5c]	103872	1		T2	3		T67	1		T19	359
valid_sources[0x5d]	110803	1		T1	1		T2	1		T7	1
valid_sources[0x5e]	86071	1		T2	7		T7	1		T19	335
valid_sources[0x5f]	284063	1		T2	6		T31	1		T7	1
valid_sources[0x60]	200437	1		T1	2		T19	377		T21	1
valid_sources[0x61]	83163	1		T2	6		T3	1		T7	3
valid_sources[0x62]	84077	1		T2	5		T19	364		T104	110
valid_sources[0x63]	220342	1		T1	2		T2	1		T19	428
valid_sources[0x64]	172727	1		T2	1		T7	2		T19	361
valid_sources[0x65]	84952	1		T1	2		T2	1		T7	1
valid_sources[0x66]	83997	1		T2	2		T7	1		T19	345
valid_sources[0x67]	86308	1		T2	1		T7	4		T19	358
valid_sources[0x68]	85064	1		T1	6		T2	5		T7	1
valid_sources[0x69]	198087	1		T1	2		T2	2		T3	1
valid_sources[0x6a]	83410	1		T2	1		T3	1		T27	23
valid_sources[0x6b]	83836	1		T1	2		T19	350		T228	5
valid_sources[0x6c]	83966	1		T2	1		T7	1		T19	328
valid_sources[0x6d]	85297	1		T1	1		T2	6		T3	2
valid_sources[0x6e]	268776	1		T2	2		T3	1		T7	2
valid_sources[0x6f]	88708	1		T2	3		T7	1		T19	405
valid_sources[0x70]	84162	1		T2	12		T3	2		T7	3
valid_sources[0x71]	177846	1		T3	1		T31	1		T19	371
valid_sources[0x72]	85596	1		T1	2		T2	2		T3	1
valid_sources[0x73]	83723	1		T2	5		T3	1		T19	340
valid_sources[0x74]	124026	1		T2	3		T37	4		T7	2
valid_sources[0x75]	126979	1		T2	1		T30	1		T7	1
valid_sources[0x76]	84662	1		T2	3		T19	338		T104	167
valid_sources[0x77]	89584	1		T2	1		T33	1		T7	2
valid_sources[0x78]	83690	1		T2	1		T67	1		T7	1
valid_sources[0x79]	84734	1		T2	5		T19	352		T105	2
valid_sources[0x7a]	83822	1		T2	5		T31	1		T7	2
valid_sources[0x7b]	325306	1		T2	1		T3	1		T7	1
valid_sources[0x7c]	89616	1		T7	1		T19	362		T228	7
valid_sources[0x7d]	157239	1		T39	1		T7	1		T19	339
valid_sources[0x7e]	239533	1		T2	5		T7	2		T19	355
valid_sources[0x7f]	114998	1		T2	3		T37	3		T19	363
valid_sources[0x80]	85632	1		T1	2		T2	2		T7	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15494681

1

T1

57

T2

75

T3

32

values[0x0]

all_enables

biggest_size

253469

1

T1

23

T2

110

T3

11

values[0x1]

all_enables

biggest_size

237599

1

T1

14

T2

51

T3

9