Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	15231868	1		T1	36		T2	556		T3	14
full_word	15986656	1		T1	94		T2	236		T3	52

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31218234	1		T1	130		T2	792		T3	66
auto[TlIntgErrCmd]	104	1		T192	8		T194	6		T224	6
auto[TlIntgErrData]	98	1		T192	4		T194	5		T224	2
auto[TlIntgErrBoth]	88	1		T192	8		T194	9		T224	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30585510	1		T1	72		T2	148		T3	35
auto[1]	633014	1		T1	58		T2	644		T3	31

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15090571	1		T1	15		T2	73		T3	3
auto[TlIntgErrNone]	partial	auto[1]	141033	1		T1	21		T2	483		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	15494813	1		T1	57		T2	75		T3	32
auto[TlIntgErrNone]	full_word	auto[1]	491817	1		T1	37		T2	161		T3	20
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T192	3		T194	3		T224	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T192	5		T194	3		T224	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T224	1		T241	1		T306	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T242	1		T241	1		T307	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T192	2		T194	2		T224	1
auto[TlIntgErrData]	partial	auto[1]	50	1		T192	2		T194	3		T243	4
auto[TlIntgErrData]	full_word	auto[0]	6	1		T224	1		T243	1		T240	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T240	1		T242	1		T305	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T192	4		T194	3		T240	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1		T192	3		T194	4		T224	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T192	1		T194	2		T240	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T224	1		T302	2		-	-