Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	512530731	11688	0	0
ep_in_enable_rd_A	512530731	3807	0	0
ep_out_enable_rd_A	512530731	4049	0	0
in_iso_rd_A	512530731	3778	0	0
intr_enable_rd_A	512530731	5142	0	0
out_iso_rd_A	512530731	3334	0	0
phy_config_rd_A	512530731	2376	0	0
phy_pins_drive_rd_A	512530731	2354	0	0
rxenable_setup_rd_A	512530731	3745	0	0
set_nak_out_rd_A	512530731	3641	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	11688	0	0
T192	56448	6	0	0
T193	6946	223	0	0
T194	114829	5	0	0
T219	4842	20	0	0
T220	3823	462	0	0
T224	22162	2	0	0
T225	4425	249	0	0
T239	8104	22	0	0
T240	38768	7	0	0
T242	19028	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	3807	0	0
T192	56448	524	0	0
T239	8104	15	0	0
T240	38768	516	0	0
T263	77864	424	0	0
T269	3100	40	0	0
T278	20808	326	0	0
T279	4611	5	0	0
T280	9563	17	0	0
T281	2659	2	0	0
T282	4668	56	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	4049	0	0
T192	56448	613	0	0
T239	8104	105	0	0
T240	38768	564	0	0
T258	4652	38	0	0
T269	3100	43	0	0
T278	20808	278	0	0
T279	4611	8	0	0
T280	9563	50	0	0
T281	2659	1	0	0
T283	6557	2	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	3778	0	0
T192	56448	470	0	0
T239	8104	113	0	0
T240	38768	561	0	0
T258	4652	3	0	0
T269	3100	8	0	0
T278	20808	361	0	0
T279	4611	46	0	0
T280	9563	10	0	0
T281	2659	43	0	0
T283	6557	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	5142	0	0
T192	56448	671	0	0
T193	6946	3	0	0
T202	2023	5	0	0
T239	8104	84	0	0
T240	38768	710	0	0
T258	4652	5	0	0
T269	3100	5	0	0
T284	1805	4	0	0
T285	3302	15	0	0
T286	3307	7	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	3334	0	0
T192	56448	335	0	0
T239	8104	72	0	0
T240	38768	440	0	0
T258	4652	4	0	0
T269	3100	4	0	0
T278	20808	108	0	0
T279	4611	12	0	0
T280	9563	15	0	0
T281	2659	4	0	0
T283	6557	1	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	2376	0	0
T192	56448	367	0	0
T239	8104	29	0	0
T240	38768	228	0	0
T258	4652	23	0	0
T269	3100	5	0	0
T278	20808	87	0	0
T279	4611	15	0	0
T280	9563	32	0	0
T281	2659	31	0	0
T283	6557	1	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	2354	0	0
T192	56448	324	0	0
T239	8104	41	0	0
T240	38768	278	0	0
T258	4652	27	0	0
T269	3100	33	0	0
T278	20808	161	0	0
T279	4611	10	0	0
T280	9563	12	0	0
T281	2659	3	0	0
T283	6557	2	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	3745	0	0
T192	56448	526	0	0
T239	8104	15	0	0
T240	38768	607	0	0
T258	4652	34	0	0
T269	3100	35	0	0
T278	20808	306	0	0
T279	4611	35	0	0
T280	9563	18	0	0
T281	2659	41	0	0
T282	4668	50	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	512530731	3641	0	0
T192	56448	571	0	0
T239	8104	77	0	0
T240	38768	495	0	0
T258	4652	30	0	0
T269	3100	4	0	0
T278	20808	267	0	0
T279	4611	51	0	0
T280	9563	8	0	0
T281	2659	5	0	0
T283	6557	10	0	0