Unified Coverage Report :: Module :: prim_reg_cdc_arb

Module : prim_reg_cdc_arb

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.24	56.67	79.07			65.22	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_control_cdc.u_arb	66.67	33.33	100.00
tb.dut.u_reg.u_wake_events_cdc.u_arb	75.84	80.00	58.14			65.22	100.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	33.33	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wake_control_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_passthru.u_dst_to_src_ack	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.84	80.00	58.14			65.22	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.08	89.80	57.14			81.40	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.40	94.12	46.15			83.33	50.00	u_wake_events_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_wr_req.u_dst_update_sync	87.50	100.00	50.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	33.33

tb.dut.u_reg.u_wake_control_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	0	1
283	0	1
284	1	1
299		unreachable

---

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :

SCORE	LINE
75.84	80.00

tb.dut.u_reg.u_wake_events_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	40	80.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	0	0.00
ALWAYS	139	6	5	83.33
ALWAYS	155	10	8	80.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	15	78.95
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	0	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	0	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	0	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	0	1
211	0	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :

SCORE	COND
66.67	100.00

tb.dut.u_reg.u_wake_control_cdc.u_arb

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :

SCORE	COND
75.84	58.14

tb.dut.u_reg.u_wake_events_cdc.u_arb

	Total	Covered	Percent
Conditions	43	25	58.14
Logical	43	25	58.14
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Not Covered

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T7,T8,T9
1	0	0	Covered	T7,T8,T9

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

---

Branch Coverage for Module : prim_reg_cdc_arb

	Line No.	Total	Covered	Percent
Branches		23	15	65.22
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	3	75.00
IF	155	6	4	66.67
CASE	197	7	4	57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T7,T8,T9
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T7,T8,T9
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T7,T8,T9
StIdle	0	0	1	-	Not Covered
StIdle	0	0	0	-	Covered	T7,T8,T9
StWait	-	-	-	1	Covered	T7,T8,T9
StWait	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	Not Covered

---

Assert Coverage for Module : prim_reg_cdc_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	6120219	631	0	2858
gen_wr_req.HwIdSelCheck_A	6120219	631	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6120219	631	0	2858
T5	5329	0	0	1
T6	2238	0	0	1
T7	3246	4	0	1
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	307	0	0	1
T18	6227	0	0	1
T19	2281	0	0	1
T20	654	0	0	1
T21	37	0	0	1
T22	10825	0	0	1
T23	1010	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6120219	631	0	0
T5	5329	0	0	0
T6	2238	0	0	0
T7	3246	4	0	0
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	307	0	0	0
T18	6227	0	0	0
T19	2281	0	0	0
T20	654	0	0	0
T21	37	0	0	0
T22	10825	0	0	0
T23	1010	0	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		3	1	33.33
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	1	100.00
CONT_ASSIGN	299	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	0	1
283	0	1
284	1	1
299		unreachable

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc.u_arb

	Total	Covered	Percent
Conditions	1	1	100.00
Logical	1	1	100.00
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Unreachable

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

	Line No.	Total	Covered	Percent
TOTAL		50	40	80.00
CONT_ASSIGN	100	1	1	100.00
ALWAYS	111	3	3	100.00
ALWAYS	121	6	4	66.67
CONT_ASSIGN	135	1	0	0.00
ALWAYS	139	6	5	83.33
ALWAYS	155	10	8	80.00
CONT_ASSIGN	183	1	1	100.00
ALWAYS	187	19	15	78.95
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
111	1	1
112	1	1
114	1	1
121	1	1
122	1	1
123	1	1
128	0	1
129	1	1
132	0	1
			MISSING_ELSE
135	0	1
139	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	0	1
			MISSING_ELSE
155	1	1
156	1	1
157	1	1
158	1	1
159	1	1
160	0	1
161	1	1
162	1	1
163	1	1
164	0	1
			MISSING_ELSE
183	1	1
187	1	1
188	1	1
192	1	1
193	1	1
195	1	1
197	1	1
199	1	1
200	1	1
202	0	1
203	0	1
204	1	1
205	1	1
206	1	1
207	1	1
210	0	1
211	0	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
			MISSING_ELSE
228	1	1
243	1	1
244	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

	Total	Covered	Percent
Conditions	43	25	58.14
Logical	43	25	58.14
Non-Logical	0	0
Event	0	0

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T7,T8,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Not Covered

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T9

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Not Covered

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T7,T8,T9
1	0	0	Covered	T7,T8,T9

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T9
1	1	Not Covered

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T7,T8,T9
1	Covered	T1,T2,T3

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Not Covered
1	1	Covered	T7,T8,T9

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T9

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

	Line No.	Total	Covered	Percent
Branches		23	15	65.22
IF	111	2	2	100.00
IF	121	4	2	50.00
IF	139	4	3	75.00
IF	155	6	4	66.67
CASE	197	7	4	57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	121	if ((!rst_dst_ni))
-2-:	123	if ((gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d))
-3-:	129	if (((dst_req_i && (!gen_wr_req.dst_req_q)) && gen_wr_req.busy))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	139	if ((!rst_dst_ni))
-2-:	141	if (gen_wr_req.dst_lat_d)
-3-:	143	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T8,T9
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	155	if ((!rst_dst_ni))
-2-:	157	if ((gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack))
-3-:	159	if ((gen_wr_req.dst_req && gen_wr_req.dst_lat_d))
-4-:	161	if (((!gen_wr_req.dst_req) && gen_wr_req.dst_lat_d))
-5-:	163	if (gen_wr_req.dst_lat_q)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T7,T8,T9
0	0	1	-	-	Not Covered
0	0	0	1	-	Covered	T7,T8,T9
0	0	0	0	1	Not Covered
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	197	case (gen_wr_req.state_q)
-2-:	200	if (gen_wr_req.dst_req)
-3-:	204	if (dst_update)
-4-:	207	if ((dst_qs_o != dst_qs_i))
-5-:	217	if (gen_wr_req.dst_update_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
StIdle	1	-	-	-	Not Covered
StIdle	0	1	-	-	Covered	T7,T8,T9
StIdle	0	0	1	-	Not Covered
StIdle	0	0	0	-	Covered	T7,T8,T9
StWait	-	-	-	1	Covered	T7,T8,T9
StWait	-	-	-	0	Covered	T7,T8,T9
default	-	-	-	-	Not Covered

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wr_req.DstUpdateReqCheck_A	6120219	631	0	2858
gen_wr_req.HwIdSelCheck_A	6120219	631	0	0

gen_wr_req.DstUpdateReqCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6120219	631	0	2858
T5	5329	0	0	1
T6	2238	0	0	1
T7	3246	4	0	1
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	307	0	0	1
T18	6227	0	0	1
T19	2281	0	0	1
T20	654	0	0	1
T21	37	0	0	1
T22	10825	0	0	1
T23	1010	0	0	1

gen_wr_req.HwIdSelCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6120219	631	0	0
T5	5329	0	0	0
T6	2238	0	0	0
T7	3246	4	0	0
T8	0	4	0	0
T9	0	4	0	0
T10	0	4	0	0
T11	0	5	0	0
T12	0	4	0	0
T13	0	5	0	0
T14	0	4	0	0
T15	0	4	0	0
T16	0	5	0	0
T17	307	0	0	0
T18	6227	0	0	0
T19	2281	0	0	0
T20	654	0	0	0
T21	37	0	0	0
T22	10825	0	0	0
T23	1010	0	0	0