Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15900796	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16674277	1		T1	7		T2	5		T3	3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31957997	1		T1	4		T2	3		T3	2
values[0x0]	308716	1		T1	4		T2	4		T3	1
values[0x1]	308360	1		T1	6		T2	5		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12677338	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	19897735	1		T1	9		T2	8		T3	8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92481	1		T8	1		T23	4		T29	13
valid_sources[0x01]	90838	1		T8	3		T23	9		T29	11
valid_sources[0x02]	93135	1		T8	2		T29	13		T4	40
valid_sources[0x03]	93399	1		T7	1		T23	1		T29	2
valid_sources[0x04]	129433	1		T8	1		T29	26		T4	50
valid_sources[0x05]	94039	1		T8	3		T23	2		T29	3
valid_sources[0x06]	125850	1		T7	1		T23	2		T29	43
valid_sources[0x07]	91572	1		T29	16		T4	54		T84	23
valid_sources[0x08]	94609	1		T7	1		T8	2		T23	11
valid_sources[0x09]	107645	1		T83	2		T29	3		T4	45
valid_sources[0x0a]	97894	1		T4	37		T84	59		T5	206
valid_sources[0x0b]	154628	1		T7	1		T21	5		T23	2
valid_sources[0x0c]	167327	1		T7	1		T8	2		T23	7
valid_sources[0x0d]	93854	1		T8	1		T23	3		T83	1
valid_sources[0x0e]	93577	1		T23	1		T29	11		T82	7
valid_sources[0x0f]	151492	1		T29	14		T4	47		T84	42
valid_sources[0x10]	92310	1		T7	1		T23	4		T29	22
valid_sources[0x11]	91534	1		T23	2		T29	29		T4	41
valid_sources[0x12]	367921	1		T23	5		T29	14		T4	57
valid_sources[0x13]	92948	1		T8	1		T23	3		T83	1
valid_sources[0x14]	91994	1		T8	2		T23	1		T29	36
valid_sources[0x15]	213396	1		T7	1		T8	2		T23	1
valid_sources[0x16]	121771	1		T23	3		T29	28		T4	56
valid_sources[0x17]	92938	1		T28	12		T83	1		T29	5
valid_sources[0x18]	122306	1		T83	2		T29	3		T4	56
valid_sources[0x19]	119743	1		T2	4		T29	44		T4	51
valid_sources[0x1a]	92141	1		T8	2		T23	2		T29	1
valid_sources[0x1b]	91369	1		T8	1		T23	4		T29	18
valid_sources[0x1c]	93236	1		T23	1		T29	6		T4	60
valid_sources[0x1d]	174309	1		T19	1		T29	21		T4	70
valid_sources[0x1e]	93514	1		T7	2		T8	2		T23	6
valid_sources[0x1f]	92447	1		T23	2		T29	2		T4	45
valid_sources[0x20]	90689	1		T3	1		T17	1		T23	6
valid_sources[0x21]	93177	1		T8	1		T23	1		T29	28
valid_sources[0x22]	93229	1		T7	1		T23	3		T83	2
valid_sources[0x23]	91638	1		T23	5		T29	6		T4	54
valid_sources[0x24]	93104	1		T8	1		T23	2		T29	24
valid_sources[0x25]	94839	1		T8	2		T23	16		T29	15
valid_sources[0x26]	102686	1		T8	1		T29	13		T4	57
valid_sources[0x27]	91489	1		T23	6		T29	59		T4	57
valid_sources[0x28]	92016	1		T8	1		T23	1		T29	3
valid_sources[0x29]	158113	1		T7	1		T8	1		T29	9
valid_sources[0x2a]	184513	1		T8	2		T23	3		T83	2
valid_sources[0x2b]	182288	1		T23	2		T29	3		T4	38
valid_sources[0x2c]	92246	1		T83	1		T29	11		T4	52
valid_sources[0x2d]	94066	1		T8	1		T23	12		T29	8
valid_sources[0x2e]	103982	1		T7	1		T8	2		T23	2
valid_sources[0x2f]	195487	1		T23	4		T29	9		T82	1
valid_sources[0x30]	92384	1		T7	1		T23	5		T24	4
valid_sources[0x31]	124590	1		T8	1		T23	15		T83	1
valid_sources[0x32]	145364	1		T23	6		T29	17		T4	59
valid_sources[0x33]	89639	1		T7	1		T23	11		T29	31
valid_sources[0x34]	89790	1		T19	1		T8	1		T29	17
valid_sources[0x35]	91136	1		T8	1		T23	2		T29	2
valid_sources[0x36]	109653	1		T8	1		T23	3		T29	26
valid_sources[0x37]	111274	1		T18	3		T8	2		T23	6
valid_sources[0x38]	92444	1		T23	15		T29	12		T4	46
valid_sources[0x39]	164402	1		T23	4		T29	17		T4	49
valid_sources[0x3a]	93762	1		T29	8		T82	1		T4	61
valid_sources[0x3b]	92114	1		T8	1		T83	1		T29	44
valid_sources[0x3c]	182717	1		T8	2		T83	1		T29	36
valid_sources[0x3d]	108476	1		T23	5		T29	5		T4	45
valid_sources[0x3e]	127627	1		T8	2		T23	1		T29	13
valid_sources[0x3f]	184449	1		T8	2		T23	14		T29	20
valid_sources[0x40]	93297	1		T8	1		T23	4		T83	1
valid_sources[0x41]	250760	1		T23	5		T83	1		T29	3
valid_sources[0x42]	93205	1		T8	1		T29	12		T4	39
valid_sources[0x43]	144385	1		T4	58		T84	41		T90	1
valid_sources[0x44]	214605	1		T8	1		T23	5		T29	2
valid_sources[0x45]	92346	1		T8	2		T29	8		T82	14
valid_sources[0x46]	94347	1		T23	1		T83	1		T29	4
valid_sources[0x47]	95559	1		T23	3		T29	8		T4	54
valid_sources[0x48]	106690	1		T7	1		T23	4		T83	1
valid_sources[0x49]	91366	1		T23	3		T83	2		T29	1
valid_sources[0x4a]	92022	1		T3	1		T7	1		T8	3
valid_sources[0x4b]	222599	1		T23	2		T29	6		T4	52
valid_sources[0x4c]	94795	1		T1	1		T3	1		T29	24
valid_sources[0x4d]	309428	1		T17	1		T23	1		T29	15
valid_sources[0x4e]	91908	1		T8	3		T23	3		T29	4
valid_sources[0x4f]	92397	1		T8	1		T23	3		T29	18
valid_sources[0x50]	116997	1		T7	3		T8	1		T23	3
valid_sources[0x51]	90863	1		T7	1		T8	4		T23	1
valid_sources[0x52]	255690	1		T8	1		T23	6		T29	3
valid_sources[0x53]	137738	1		T7	2		T8	1		T23	1
valid_sources[0x54]	215134	1		T8	3		T23	14		T29	5
valid_sources[0x55]	123135	1		T23	3		T29	6		T82	2
valid_sources[0x56]	193919	1		T7	1		T8	1		T23	3
valid_sources[0x57]	93160	1		T7	1		T8	1		T23	3
valid_sources[0x58]	367240	1		T23	1		T29	12		T4	73
valid_sources[0x59]	149916	1		T19	5		T8	3		T23	3
valid_sources[0x5a]	92351	1		T8	1		T23	1		T29	15
valid_sources[0x5b]	229394	1		T8	2		T23	3		T29	15
valid_sources[0x5c]	92275	1		T8	2		T23	2		T83	1
valid_sources[0x5d]	92328	1		T8	2		T23	1		T29	7
valid_sources[0x5e]	239664	1		T18	2		T8	2		T23	5
valid_sources[0x5f]	90279	1		T8	1		T83	1		T29	6
valid_sources[0x60]	94019	1		T23	4		T29	11		T4	44
valid_sources[0x61]	195589	1		T23	3		T29	10		T4	40
valid_sources[0x62]	90337	1		T29	27		T82	17		T4	38
valid_sources[0x63]	108941	1		T23	1		T4	45		T84	21
valid_sources[0x64]	92261	1		T23	5		T29	4		T4	70
valid_sources[0x65]	92154	1		T23	4		T29	1		T4	47
valid_sources[0x66]	151772	1		T23	4		T29	11		T82	4
valid_sources[0x67]	92375	1		T8	2		T23	4		T83	2
valid_sources[0x68]	89592	1		T29	25		T4	44		T84	19
valid_sources[0x69]	90445	1		T7	1		T8	1		T23	2
valid_sources[0x6a]	118012	1		T8	3		T23	2		T29	28
valid_sources[0x6b]	91887	1		T8	1		T23	1		T29	6
valid_sources[0x6c]	310485	1		T7	2		T29	22		T4	44
valid_sources[0x6d]	108564	1		T8	1		T23	2		T29	1
valid_sources[0x6e]	91565	1		T8	1		T23	1		T29	44
valid_sources[0x6f]	93841	1		T7	1		T8	1		T23	3
valid_sources[0x70]	109171	1		T8	2		T23	2		T29	5
valid_sources[0x71]	126682	1		T23	2		T29	14		T4	59
valid_sources[0x72]	91340	1		T23	7		T83	1		T29	9
valid_sources[0x73]	157801	1		T7	2		T8	1		T23	5
valid_sources[0x74]	89609	1		T8	1		T23	5		T29	8
valid_sources[0x75]	230294	1		T23	1		T29	2		T82	2
valid_sources[0x76]	92926	1		T1	6		T29	3		T4	62
valid_sources[0x77]	91388	1		T7	1		T23	1		T29	13
valid_sources[0x78]	93690	1		T3	1		T8	1		T23	15
valid_sources[0x79]	318542	1		T8	2		T23	3		T83	1
valid_sources[0x7a]	283507	1		T8	2		T29	8		T4	59
valid_sources[0x7b]	357470	1		T23	1		T29	20		T4	52
valid_sources[0x7c]	90933	1		T23	1		T29	6		T4	47
valid_sources[0x7d]	91651	1		T8	1		T23	4		T29	4
valid_sources[0x7e]	109298	1		T7	1		T8	2		T23	3
valid_sources[0x7f]	92269	1		T23	3		T83	1		T29	8
valid_sources[0x80]	92678	1		T23	9		T29	22		T4	51

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16181185

1

T1

1

T2

1

T3

1

values[0x0]

all_enables

biggest_size

254548

1

T1

2

T2

3

T3

1

values[0x1]

all_enables

biggest_size

238544

1

T1

4

T2

1

T3

1