Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 15915247 1 T1 7 T2 7 T3 7
full_word 16675236 1 T1 7 T2 5 T3 3



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 32590153 1 T1 14 T2 12 T3 10
auto[TlIntgErrCmd] 125 1 T191 5 T192 5 T193 3
auto[TlIntgErrData] 97 1 T191 8 T192 2 T193 2
auto[TlIntgErrBoth] 108 1 T191 7 T192 3 T193 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31959754 1 T1 4 T2 3 T3 2
auto[1] 630729 1 T1 10 T2 9 T3 8



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 15778245 1 T1 3 T2 2 T3 1
auto[TlIntgErrNone] partial auto[1] 136698 1 T1 4 T2 5 T3 6
auto[TlIntgErrNone] full_word auto[0] 16181354 1 T1 1 T2 1 T3 1
auto[TlIntgErrNone] full_word auto[1] 493856 1 T1 6 T2 4 T3 2
auto[TlIntgErrCmd] partial auto[0] 54 1 T191 3 T192 3 T193 1
auto[TlIntgErrCmd] partial auto[1] 60 1 T191 1 T192 2 T193 1
auto[TlIntgErrCmd] full_word auto[0] 6 1 T191 1 T233 1 T286 1
auto[TlIntgErrCmd] full_word auto[1] 5 1 T193 1 T285 1 T287 1
auto[TlIntgErrData] partial auto[0] 45 1 T191 3 T192 1 T193 1
auto[TlIntgErrData] partial auto[1] 41 1 T191 4 T192 1 T193 1
auto[TlIntgErrData] full_word auto[0] 6 1 T191 1 T285 1 T287 1
auto[TlIntgErrData] full_word auto[1] 5 1 T286 1 T284 1 T288 1
auto[TlIntgErrBoth] partial auto[0] 42 1 T191 3 T192 1 T193 1
auto[TlIntgErrBoth] partial auto[1] 62 1 T191 4 T192 2 T193 4
auto[TlIntgErrBoth] full_word auto[0] 2 1 T285 1 T289 1 - -
auto[TlIntgErrBoth] full_word auto[1] 2 1 T288 1 T289 1 - -

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