Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.73	97.53	86.57	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506346061	11074	0	0
ep_in_enable_rd_A	506346061	1689	0	0
ep_out_enable_rd_A	506346061	2037	0	0
in_iso_rd_A	506346061	1692	0	0
intr_enable_rd_A	506346061	2739	0	0
out_iso_rd_A	506346061	1962	0	0
phy_config_rd_A	506346061	1105	0	0
phy_pins_drive_rd_A	506346061	1595	0	0
rxenable_setup_rd_A	506346061	1803	0	0
set_nak_out_rd_A	506346061	1954	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	11074	0	0
T191	39540	8	0	0
T192	12215	1	0	0
T193	12206	1	0	0
T218	7146	436	0	0
T219	5443	8	0	0
T220	6742	5	0	0
T225	2346	234	0	0
T226	16277	723	0	0
T229	10022	27	0	0
T235	4820	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1689	0	0
T191	39540	215	0	0
T219	5443	20	0	0
T220	6742	7	0	0
T229	10022	77	0	0
T233	39735	214	0	0
T235	4820	1	0	0
T250	16999	98	0	0
T251	17837	204	0	0
T263	6532	39	0	0
T264	2579	4	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	2037	0	0
T191	39540	256	0	0
T219	5443	9	0	0
T220	6742	59	0	0
T229	10022	53	0	0
T233	39735	297	0	0
T235	4820	5	0	0
T250	16999	111	0	0
T251	17837	225	0	0
T263	6532	30	0	0
T264	2579	31	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1692	0	0
T191	39540	316	0	0
T219	5443	1	0	0
T220	6742	1	0	0
T226	16277	1	0	0
T229	10022	14	0	0
T233	39735	253	0	0
T235	4820	28	0	0
T250	16999	86	0	0
T263	6532	16	0	0
T264	2579	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	2739	0	0
T191	39540	320	0	0
T204	3102	12	0	0
T219	5443	10	0	0
T220	6742	2	0	0
T229	10022	122	0	0
T233	39735	492	0	0
T235	4820	5	0	0
T250	16999	102	0	0
T270	3882	37	0	0
T271	2253	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1962	0	0
T191	39540	257	0	0
T219	5443	7	0	0
T220	6742	44	0	0
T226	16277	3	0	0
T229	10022	16	0	0
T233	39735	337	0	0
T235	4820	3	0	0
T250	16999	116	0	0
T263	6532	4	0	0
T264	2579	41	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1105	0	0
T191	39540	162	0	0
T220	6742	7	0	0
T229	10022	70	0	0
T233	39735	104	0	0
T235	4820	2	0	0
T250	16999	90	0	0
T251	17837	204	0	0
T263	6532	23	0	0
T264	2579	8	0	0
T272	44589	38	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1595	0	0
T191	39540	301	0	0
T219	5443	29	0	0
T220	6742	1	0	0
T229	10022	25	0	0
T233	39735	189	0	0
T235	4820	3	0	0
T250	16999	102	0	0
T251	17837	198	0	0
T263	6532	33	0	0
T272	44589	122	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1803	0	0
T191	39540	167	0	0
T219	5443	2	0	0
T220	6742	48	0	0
T229	10022	114	0	0
T233	39735	260	0	0
T235	4820	47	0	0
T250	16999	90	0	0
T251	17837	194	0	0
T263	6532	34	0	0
T264	2579	7	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506346061	1954	0	0
T191	39540	355	0	0
T219	5443	27	0	0
T220	6742	8	0	0
T229	10022	50	0	0
T233	39735	248	0	0
T235	4820	45	0	0
T250	16999	113	0	0
T251	17837	183	0	0
T263	6532	7	0	0
T264	2579	4	0	0