Module Definition
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Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_se0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.22 100.00 66.67 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
72.22 100.00 66.67 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dn


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 13293084 13281387 0 0
selKnown1 104 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 13293084 13281387 0 0
T1 42 37 0 0
T2 290 285 0 0
T3 2 0 0 0
T7 125 120 0 0
T8 387 382 0 0
T17 22 17 0 0
T18 444 439 0 0
T19 2 0 0 0
T20 374 369 0 0
T21 114 333 0 0
T22 2079 5482 0 0
T24 8 17 0 0
T28 0 2 0 0
T29 0 410 0 0
T30 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 104 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T7
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT25,T26,T27
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T7

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144791 142678 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144791 142678 0 0
T1 2 1 0 0
T2 2 1 0 0
T7 2 1 0 0
T8 2 1 0 0
T17 1 0 0 0
T18 2 1 0 0
T20 2 1 0 0
T21 2 1 0 0
T22 189 188 0 0
T24 1 0 0 0
T28 0 1 0 0
T29 0 205 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9666.67
Logical9666.67
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T7
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT25,T26,T27
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT1,T2,T7
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4341757 4339079 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4341757 4339079 0 0
T1 13 12 0 0
T2 96 95 0 0
T3 1 0 0 0
T7 41 40 0 0
T8 128 127 0 0
T17 7 6 0 0
T18 147 146 0 0
T19 1 0 0 0
T20 124 123 0 0
T21 0 111 0 0
T22 0 1703 0 0
T24 0 6 0 0
T30 1 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T7
10CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10Not Covered
11CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T7

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144792 142678 0 0
selKnown1 50 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144792 142678 0 0
T1 2 1 0 0
T2 2 1 0 0
T7 2 1 0 0
T8 2 1 0 0
T17 1 0 0 0
T18 2 1 0 0
T20 2 1 0 0
T21 2 1 0 0
T22 189 188 0 0
T24 1 0 0 0
T28 0 1 0 0
T29 0 205 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T7
10CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT31,T32,T33
11CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T7

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4319987 4317873 0 0
selKnown1 28 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4319987 4317873 0 0
T1 12 11 0 0
T2 94 93 0 0
T7 39 38 0 0
T8 127 126 0 0
T17 6 5 0 0
T18 146 145 0 0
T20 122 121 0 0
T21 110 109 0 0
T22 1701 1700 0 0
T24 6 5 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 28 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T7
01CoveredT1,T2,T3
10CoveredT25,T27,T34

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T27,T34
10CoveredT26,T35,T36
11CoveredT25,T27,T34

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT1,T2,T7
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 4341757 4339079 0 0
selKnown1 26 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 4341757 4339079 0 0
T1 13 12 0 0
T2 96 95 0 0
T3 1 0 0 0
T7 41 40 0 0
T8 128 127 0 0
T17 7 6 0 0
T18 147 146 0 0
T19 1 0 0 0
T20 124 123 0 0
T21 0 111 0 0
T22 0 1703 0 0
T24 0 6 0 0
T30 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 26 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%