Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14726396	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	15546627	1		T1	9603		T2	11		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29630554	1		T1	13824		T2	947		T3	63
values[0x0]	320865	1		T1	1381		T2	9		T3	4
values[0x1]	321604	1		T1	1367		T2	9		T3	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	11736799	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	18536224	1		T1	10942		T2	315		T3	34

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	140025	1		T1	52		T2	1		T21	107
valid_sources[0x01]	84009	1		T1	130		T2	3		T19	1
valid_sources[0x02]	84864	1		T1	36		T2	7		T21	91
valid_sources[0x03]	86250	1		T1	48		T2	4		T21	79
valid_sources[0x04]	86229	1		T1	64		T2	9		T19	1
valid_sources[0x05]	85571	1		T1	106		T2	4		T21	98
valid_sources[0x06]	112608	1		T1	150		T2	2		T21	70
valid_sources[0x07]	91769	1		T1	56		T2	2		T21	70
valid_sources[0x08]	96822	1		T1	142		T2	3		T19	4
valid_sources[0x09]	85452	1		T1	101		T2	3		T14	1
valid_sources[0x0a]	85529	1		T1	70		T2	2		T17	2
valid_sources[0x0b]	84223	1		T1	35		T2	1		T19	1
valid_sources[0x0c]	171852	1		T1	36		T2	5		T17	1
valid_sources[0x0d]	130890	1		T1	59		T2	2		T19	1
valid_sources[0x0e]	86348	1		T1	43		T2	5		T21	87
valid_sources[0x0f]	85813	1		T1	52		T2	5		T14	1
valid_sources[0x10]	228007	1		T1	57		T2	1		T19	2
valid_sources[0x11]	237467	1		T1	50		T2	5		T21	101
valid_sources[0x12]	85680	1		T1	36		T2	8		T3	1
valid_sources[0x13]	86774	1		T1	86		T2	2		T21	68
valid_sources[0x14]	114377	1		T1	57		T2	2		T17	1
valid_sources[0x15]	86230	1		T1	82		T2	3		T3	1
valid_sources[0x16]	84462	1		T1	81		T2	7		T18	2
valid_sources[0x17]	87003	1		T1	38		T2	2		T19	1
valid_sources[0x18]	87875	1		T1	71		T2	4		T19	1
valid_sources[0x19]	84420	1		T1	55		T2	6		T21	116
valid_sources[0x1a]	117645	1		T1	64		T2	3		T3	1
valid_sources[0x1b]	102570	1		T1	45		T2	7		T19	1
valid_sources[0x1c]	85221	1		T1	79		T2	5		T19	1
valid_sources[0x1d]	83736	1		T1	50		T2	4		T21	103
valid_sources[0x1e]	144215	1		T1	62		T2	6		T21	99
valid_sources[0x1f]	84950	1		T1	36		T2	3		T3	2
valid_sources[0x20]	108729	1		T1	58		T2	2		T17	2
valid_sources[0x21]	94971	1		T1	79		T2	3		T3	1
valid_sources[0x22]	97147	1		T1	60		T2	5		T3	1
valid_sources[0x23]	85674	1		T1	67		T2	2		T3	1
valid_sources[0x24]	110127	1		T1	33		T2	3		T19	1
valid_sources[0x25]	114197	1		T1	69		T2	3		T19	1
valid_sources[0x26]	84795	1		T1	87		T2	7		T16	1
valid_sources[0x27]	86551	1		T1	94		T2	8		T3	1
valid_sources[0x28]	85596	1		T1	52		T2	7		T21	87
valid_sources[0x29]	84222	1		T1	57		T2	5		T21	78
valid_sources[0x2a]	142267	1		T1	104		T2	2		T19	3
valid_sources[0x2b]	82966	1		T1	25		T2	6		T17	1
valid_sources[0x2c]	242109	1		T1	63		T2	3		T21	93
valid_sources[0x2d]	86114	1		T1	67		T2	5		T21	120
valid_sources[0x2e]	118696	1		T1	39		T2	6		T21	81
valid_sources[0x2f]	85583	1		T1	102		T2	1		T19	2
valid_sources[0x30]	144937	1		T1	46		T2	3		T19	1
valid_sources[0x31]	86427	1		T1	77		T2	1		T3	1
valid_sources[0x32]	83788	1		T1	48		T2	3		T14	1
valid_sources[0x33]	85217	1		T1	70		T2	2		T19	2
valid_sources[0x34]	116977	1		T1	97		T2	6		T19	3
valid_sources[0x35]	83461	1		T1	52		T2	2		T15	1
valid_sources[0x36]	85099	1		T1	43		T2	5		T19	1
valid_sources[0x37]	84717	1		T1	129		T3	1		T19	1
valid_sources[0x38]	90727	1		T1	76		T2	2		T21	76
valid_sources[0x39]	203578	1		T1	61		T2	2		T21	77
valid_sources[0x3a]	85601	1		T1	39		T2	7		T21	94
valid_sources[0x3b]	235153	1		T1	54		T21	102		T4	106
valid_sources[0x3c]	203057	1		T1	42		T2	6		T3	4
valid_sources[0x3d]	85338	1		T1	89		T2	6		T3	2
valid_sources[0x3e]	85055	1		T1	89		T2	3		T3	1
valid_sources[0x3f]	84519	1		T1	64		T2	4		T21	74
valid_sources[0x40]	131726	1		T1	70		T2	5		T21	79
valid_sources[0x41]	83840	1		T1	66		T2	6		T15	1
valid_sources[0x42]	118801	1		T1	62		T2	4		T19	1
valid_sources[0x43]	213605	1		T1	58		T2	6		T19	2
valid_sources[0x44]	85435	1		T1	56		T2	5		T3	1
valid_sources[0x45]	166277	1		T1	77		T2	4		T3	1
valid_sources[0x46]	129422	1		T1	32		T2	3		T19	4
valid_sources[0x47]	120207	1		T1	75		T2	4		T21	91
valid_sources[0x48]	106024	1		T1	41		T2	3		T21	85
valid_sources[0x49]	84976	1		T1	116		T2	3		T3	1
valid_sources[0x4a]	197939	1		T1	92		T2	3		T19	1
valid_sources[0x4b]	84476	1		T1	74		T2	4		T18	1
valid_sources[0x4c]	85201	1		T1	80		T2	3		T19	3
valid_sources[0x4d]	247382	1		T1	20		T2	4		T3	1
valid_sources[0x4e]	85305	1		T1	54		T2	7		T19	1
valid_sources[0x4f]	84825	1		T1	47		T2	5		T19	2
valid_sources[0x50]	287274	1		T1	42		T2	3		T19	5
valid_sources[0x51]	87927	1		T1	57		T2	5		T21	88
valid_sources[0x52]	84648	1		T1	49		T2	3		T19	1
valid_sources[0x53]	86162	1		T1	40		T2	7		T19	1
valid_sources[0x54]	86237	1		T1	50		T2	7		T3	1
valid_sources[0x55]	85691	1		T1	43		T2	3		T19	1
valid_sources[0x56]	85849	1		T1	121		T2	3		T19	3
valid_sources[0x57]	85228	1		T1	36		T2	3		T19	4
valid_sources[0x58]	84973	1		T1	106		T2	3		T17	1
valid_sources[0x59]	84892	1		T1	43		T2	4		T21	95
valid_sources[0x5a]	145293	1		T1	55		T2	5		T19	1
valid_sources[0x5b]	84885	1		T1	78		T2	5		T3	1
valid_sources[0x5c]	84870	1		T1	30		T2	3		T16	1
valid_sources[0x5d]	88891	1		T1	83		T2	6		T21	74
valid_sources[0x5e]	198001	1		T1	86		T2	3		T19	1
valid_sources[0x5f]	85827	1		T1	36		T2	6		T19	1
valid_sources[0x60]	85861	1		T1	43		T2	1		T19	2
valid_sources[0x61]	86537	1		T1	49		T2	2		T19	1
valid_sources[0x62]	85044	1		T1	51		T2	7		T3	1
valid_sources[0x63]	94345	1		T1	73		T2	3		T21	91
valid_sources[0x64]	85345	1		T1	33		T2	2		T19	1
valid_sources[0x65]	88380	1		T1	83		T2	3		T3	1
valid_sources[0x66]	125645	1		T1	77		T2	1		T3	1
valid_sources[0x67]	85690	1		T1	108		T2	7		T16	2
valid_sources[0x68]	84574	1		T1	82		T2	5		T3	1
valid_sources[0x69]	117326	1		T1	37		T2	3		T19	3
valid_sources[0x6a]	161940	1		T1	70		T2	2		T3	1
valid_sources[0x6b]	547712	1		T1	64		T2	8		T19	1
valid_sources[0x6c]	87406	1		T1	44		T2	3		T19	4
valid_sources[0x6d]	83822	1		T1	89		T2	3		T19	1
valid_sources[0x6e]	200811	1		T1	35		T2	5		T15	3
valid_sources[0x6f]	405028	1		T1	101		T2	4		T19	2
valid_sources[0x70]	85964	1		T1	105		T2	3		T21	108
valid_sources[0x71]	110297	1		T1	46		T2	2		T21	95
valid_sources[0x72]	85361	1		T1	59		T2	3		T21	73
valid_sources[0x73]	83271	1		T1	67		T2	2		T21	67
valid_sources[0x74]	85506	1		T1	73		T2	4		T3	1
valid_sources[0x75]	173203	1		T1	70		T2	4		T19	4
valid_sources[0x76]	87150	1		T1	67		T2	3		T19	2
valid_sources[0x77]	85386	1		T1	61		T2	2		T21	67
valid_sources[0x78]	125275	1		T1	109		T2	4		T3	4
valid_sources[0x79]	107521	1		T1	44		T2	3		T21	89
valid_sources[0x7a]	85354	1		T1	43		T2	5		T3	1
valid_sources[0x7b]	257080	1		T1	94		T2	7		T19	6
valid_sources[0x7c]	243647	1		T1	61		T2	4		T19	3
valid_sources[0x7d]	87044	1		T1	92		T2	2		T3	3
valid_sources[0x7e]	85414	1		T1	91		T2	4		T21	88
valid_sources[0x7f]	129826	1		T1	86		T2	4		T18	4
valid_sources[0x80]	84406	1		T1	49		T2	1		T17	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15029389

1

T1

6910

T2

2

T14

1

values[0x0]

all_enables

biggest_size

266367

1

T1

1356

T2

6

T3

3

values[0x1]

all_enables

biggest_size

250871

1

T1

1337

T2

3

T3

5