Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	14741890	1		T1	6969		T2	954		T3	73
full_word	15547684	1		T1	9603		T2	11		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30289284	1		T1	16572		T2	965		T3	81
auto[TlIntgErrCmd]	95	1		T185	5		T208	3		T215	5
auto[TlIntgErrData]	92	1		T185	2		T208	3		T215	9
auto[TlIntgErrBoth]	103	1		T185	3		T208	4		T215	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29632634	1		T1	13824		T2	947		T3	63
auto[1]	656940	1		T1	2748		T2	18		T3	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	14602915	1		T1	6914		T2	945		T3	63
auto[TlIntgErrNone]	partial	auto[1]	138702	1		T1	55		T2	9		T3	10
auto[TlIntgErrNone]	full_word	auto[0]	15029577	1		T1	6910		T2	2		T14	1
auto[TlIntgErrNone]	full_word	auto[1]	518090	1		T1	2693		T2	9		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T185	1		T208	3		T215	1
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T185	3		T215	3		T224	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T185	1		T224	1		T291	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T215	1		T292	1		-	-
auto[TlIntgErrData]	partial	auto[0]	50	1		T185	1		T208	1		T215	7
auto[TlIntgErrData]	partial	auto[1]	39	1		T185	1		T208	2		T215	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T289	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T289	1		T290	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	49	1		T185	2		T208	2		T215	2
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T185	1		T208	2		T215	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T288	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T289	1		T293	1		T294	1