Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	506087362	12816	0	0
ep_in_enable_rd_A	506087362	2237	0	0
ep_out_enable_rd_A	506087362	2205	0	0
in_iso_rd_A	506087362	2242	0	0
intr_enable_rd_A	506087362	2849	0	0
out_iso_rd_A	506087362	2111	0	0
phy_config_rd_A	506087362	1442	0	0
phy_pins_drive_rd_A	506087362	1631	0	0
rxenable_setup_rd_A	506087362	2494	0	0
set_nak_out_rd_A	506087362	2427	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	12816	0	0
T185	29762	1	0	0
T186	6368	3	0	0
T187	9083	322	0	0
T207	4369	4	0	0
T208	18367	2	0	0
T213	6572	196	0	0
T214	5419	769	0	0
T215	49405	4	0	0
T217	11725	702	0	0
T220	6406	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2237	0	0
T185	29762	251	0	0
T207	4369	52	0	0
T225	35968	236	0	0
T244	3716	87	0	0
T256	8014	27	0	0
T257	9242	4	0	0
T259	3138	43	0	0
T267	8159	38	0	0
T268	5876	10	0	0
T269	9902	28	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2205	0	0
T185	29762	185	0	0
T207	4369	9	0	0
T225	35968	218	0	0
T244	3716	18	0	0
T256	8014	15	0	0
T257	9242	45	0	0
T259	3138	58	0	0
T267	8159	11	0	0
T268	5876	9	0	0
T270	7760	40	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2242	0	0
T185	29762	261	0	0
T207	4369	7	0	0
T225	35968	272	0	0
T244	3716	90	0	0
T256	8014	31	0	0
T257	9242	57	0	0
T259	3138	1	0	0
T267	8159	17	0	0
T268	5876	11	0	0
T270	7760	5	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2849	0	0
T185	29762	295	0	0
T207	4369	10	0	0
T244	3716	76	0	0
T256	8014	28	0	0
T257	9242	22	0	0
T259	3138	1	0	0
T271	1741	14	0	0
T272	3247	6	0	0
T273	2490	13	0	0
T274	4183	33	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2111	0	0
T185	29762	179	0	0
T187	9083	1	0	0
T207	4369	8	0	0
T213	6572	4	0	0
T225	35968	195	0	0
T244	3716	67	0	0
T256	8014	19	0	0
T257	9242	19	0	0
T259	3138	49	0	0
T267	8159	33	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	1442	0	0
T185	29762	89	0	0
T207	4369	15	0	0
T225	35968	157	0	0
T244	3716	29	0	0
T256	8014	33	0	0
T257	9242	32	0	0
T259	3138	17	0	0
T267	8159	20	0	0
T268	5876	3	0	0
T270	7760	9	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	1631	0	0
T185	29762	277	0	0
T207	4369	4	0	0
T225	35968	167	0	0
T244	3716	11	0	0
T256	8014	15	0	0
T257	9242	19	0	0
T259	3138	29	0	0
T267	8159	8	0	0
T268	5876	6	0	0
T269	9902	15	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2494	0	0
T185	29762	246	0	0
T207	4369	10	0	0
T225	35968	337	0	0
T244	3716	88	0	0
T256	8014	50	0	0
T257	9242	27	0	0
T259	3138	65	0	0
T267	8159	9	0	0
T268	5876	7	0	0
T270	7760	50	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	506087362	2427	0	0
T185	29762	378	0	0
T207	4369	8	0	0
T225	35968	270	0	0
T244	3716	5	0	0
T256	8014	20	0	0
T257	9242	74	0	0
T259	3138	58	0	0
T267	8159	5	0	0
T268	5876	9	0	0
T270	7760	23	0	0