Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_reg_cdc
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.43 100.00 85.71 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_wake_events_cdc 68.40 94.12 46.15 83.33 50.00
tb.dut.u_reg.u_wake_control_cdc 97.73 100.00 90.91 100.00 100.00



Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.40 94.12 46.15 83.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.94 90.62 52.94 84.21 60.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.47 99.76 98.11 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 82.08 89.80 57.14 81.40 100.00
u_src_to_dst_req 56.41 92.31 33.33 100.00 0.00



Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.73 100.00 90.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.13 96.08 96.43 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.47 99.76 98.11 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_arb 96.88 87.50 100.00 100.00 100.00
u_src_to_dst_req 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Module : prim_reg_cdc
TotalCoveredPercent
Conditions141285.71
Logical141285.71
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T6
10CoveredT2,T3,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

Branch Coverage for Module : prim_reg_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T6
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T6
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_reg_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 1012174724 304113 0 0
DstReqKnown_A 12127126 12077354 0 0
SrcAckBusyChk_A 1012174724 1135 0 0
SrcBusyKnown_A 1012174724 1011679828 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1012174724 304113 0 0
T2 171832 1352 0 0
T3 643901 375 0 0
T6 0 350 0 0
T7 0 237 0 0
T8 0 472 0 0
T9 0 474 0 0
T10 0 634 0 0
T11 0 416 0 0
T12 0 417 0 0
T13 0 598 0 0
T14 11015 0 0 0
T15 9332 0 0 0
T16 11521 0 0 0
T17 7690 0 0 0
T18 160983 0 0 0
T19 43225 0 0 0
T20 7100 0 0 0
T21 582627 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 12127126 12077354 0 0
T1 11226 11214 0 0
T2 1316 1296 0 0
T3 18994 18978 0 0
T14 358 346 0 0
T15 150 132 0 0
T16 260 244 0 0
T17 158 138 0 0
T18 1300 1280 0 0
T19 756 738 0 0
T20 194 178 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1012174724 1135 0 0
T2 171832 2 0 0
T3 643901 2 0 0
T6 0 2 0 0
T7 0 2 0 0
T8 0 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 11015 0 0 0
T15 9332 0 0 0
T16 11521 0 0 0
T17 7690 0 0 0
T18 160983 0 0 0
T19 43225 0 0 0
T20 7100 0 0 0
T21 582627 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1012174724 1011679828 0 0
T1 730234 730078 0 0
T2 343664 343552 0 0
T3 1287802 1287696 0 0
T14 22030 21912 0 0
T15 18664 18486 0 0
T16 23042 22910 0 0
T17 15380 15222 0 0
T18 321966 321776 0 0
T19 86450 86342 0 0
T20 14200 14098 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
TOTAL171694.12
CONT_ASSIGN6500
ALWAYS715480.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11577100.00
CONT_ASSIGN15000
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 unreachable
71 1 1
72 1 1
73 1 1
74 unreachable
75 1 1
76 0 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 unreachable
124 unreachable
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 unreachable
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalCoveredPercent
Conditions13646.15
Logical13646.15
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T6
10Not Covered

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
Line No.TotalCoveredPercent
Branches 6 5 83.33
IF 71 3 2 66.67
IF 115 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Unreachable
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 2 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 2 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 506087362 0 0 0
DstReqKnown_A 6063563 6038677 0 0
SrcAckBusyChk_A 506087362 0 0 0
SrcBusyKnown_A 506087362 505839914 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6063563 6038677 0 0
T1 5613 5607 0 0
T2 658 648 0 0
T3 9497 9489 0 0
T14 179 173 0 0
T15 75 66 0 0
T16 130 122 0 0
T17 79 69 0 0
T18 650 640 0 0
T19 378 369 0 0
T20 97 89 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 505839914 0 0
T1 365117 365039 0 0
T2 171832 171776 0 0
T3 643901 643848 0 0
T14 11015 10956 0 0
T15 9332 9243 0 0
T16 11521 11455 0 0
T17 7690 7611 0 0
T18 160983 160888 0 0
T19 43225 43171 0 0
T20 7100 7049 0 0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
TOTAL2222100.00
CONT_ASSIGN6511100.00
ALWAYS7166100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN10911100.00
ALWAYS11599100.00
CONT_ASSIGN15011100.00
CONT_ASSIGN15511100.00
CONT_ASSIGN15611100.00
CONT_ASSIGN20011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
65 1 1
71 1 1
72 1 1
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
85 1 1
109 1 1
115 1 1
116 1 1
117 1 1
118 1 1
123 1 1
124 1 1
125 1 1
134 1 1
135 1 1
MISSING_ELSE
150 1 1
155 1 1
156 1 1
200 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalCoveredPercent
Conditions111090.91
Logical111090.91
Non-Logical00
Event00

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T6

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT2,T3,T6

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T6
11CoveredT2,T3,T6

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11Unreachable

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 71 4 4 100.00
IF 115 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 71 if ((!rst_src_ni)) -2-: 73 if (src_req) -3-: 75 if (src_ack)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T6
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 115 if ((!rst_src_ni)) -2-: 118 if (src_req) -3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T6
0 0 1 Covered T2,T3,T6
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BusySrcReqChk_A 506087362 304113 0 0
DstReqKnown_A 6063563 6038677 0 0
SrcAckBusyChk_A 506087362 1135 0 0
SrcBusyKnown_A 506087362 505839914 0 0


BusySrcReqChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 304113 0 0
T2 171832 1352 0 0
T3 643901 375 0 0
T6 0 350 0 0
T7 0 237 0 0
T8 0 472 0 0
T9 0 474 0 0
T10 0 634 0 0
T11 0 416 0 0
T12 0 417 0 0
T13 0 598 0 0
T14 11015 0 0 0
T15 9332 0 0 0
T16 11521 0 0 0
T17 7690 0 0 0
T18 160983 0 0 0
T19 43225 0 0 0
T20 7100 0 0 0
T21 582627 0 0 0

DstReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6063563 6038677 0 0
T1 5613 5607 0 0
T2 658 648 0 0
T3 9497 9489 0 0
T14 179 173 0 0
T15 75 66 0 0
T16 130 122 0 0
T17 79 69 0 0
T18 650 640 0 0
T19 378 369 0 0
T20 97 89 0 0

SrcAckBusyChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 1135 0 0
T2 171832 2 0 0
T3 643901 2 0 0
T6 0 2 0 0
T7 0 2 0 0
T8 0 2 0 0
T9 0 2 0 0
T10 0 2 0 0
T11 0 2 0 0
T12 0 2 0 0
T13 0 2 0 0
T14 11015 0 0 0
T15 9332 0 0 0
T16 11521 0 0 0
T17 7690 0 0 0
T18 160983 0 0 0
T19 43225 0 0 0
T20 7100 0 0 0
T21 582627 0 0 0

SrcBusyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 506087362 505839914 0 0
T1 365117 365039 0 0
T2 171832 171776 0 0
T3 643901 643848 0 0
T14 11015 10956 0 0
T15 9332 9243 0 0
T16 11521 11455 0 0
T17 7690 7611 0 0
T18 160983 160888 0 0
T19 43225 43171 0 0
T20 7100 7049 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%