Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16313503	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17135357	1		T1	8		T2	9		T3	23

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32788796	1		T1	5		T2	10		T3	21
values[0x0]	329855	1		T1	6		T2	7		T3	4
values[0x1]	330209	1		T1	5		T2	9		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13006879	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20441981	1		T1	10		T2	14		T3	24

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	97361	1		T31	1		T4	63		T5	553
valid_sources[0x01]	97552	1		T33	1		T4	92		T5	595
valid_sources[0x02]	96014	1		T33	1		T4	82		T5	625
valid_sources[0x03]	97695	1		T4	84		T5	581		T111	1
valid_sources[0x04]	98562	1		T33	1		T4	61		T5	547
valid_sources[0x05]	97858	1		T33	2		T35	1		T4	87
valid_sources[0x06]	97117	1		T4	88		T36	2		T5	540
valid_sources[0x07]	249780	1		T33	4		T4	73		T108	5
valid_sources[0x08]	132163	1		T33	2		T4	83		T5	540
valid_sources[0x09]	100386	1		T33	5		T4	83		T108	2
valid_sources[0x0a]	97613	1		T33	1		T4	57		T5	599
valid_sources[0x0b]	97324	1		T4	76		T5	604		T60	6
valid_sources[0x0c]	99688	1		T33	1		T4	80		T108	2
valid_sources[0x0d]	98138	1		T33	103		T4	68		T5	599
valid_sources[0x0e]	98228	1		T33	550		T4	72		T5	561
valid_sources[0x0f]	181897	1		T3	1		T4	74		T5	614
valid_sources[0x10]	96991	1		T33	1		T4	91		T5	626
valid_sources[0x11]	96234	1		T4	69		T108	2		T5	604
valid_sources[0x12]	138234	1		T1	1		T33	2		T4	80
valid_sources[0x13]	260204	1		T33	2		T4	97		T5	590
valid_sources[0x14]	99222	1		T33	4		T4	80		T5	594
valid_sources[0x15]	120463	1		T33	2		T35	3		T4	80
valid_sources[0x16]	96987	1		T4	72		T5	537		T60	2
valid_sources[0x17]	98811	1		T2	1		T33	85		T109	1
valid_sources[0x18]	244228	1		T4	80		T5	611		T111	1
valid_sources[0x19]	180609	1		T4	76		T36	1		T5	544
valid_sources[0x1a]	96063	1		T4	63		T5	532		T110	1
valid_sources[0x1b]	97084	1		T33	1		T35	1		T4	83
valid_sources[0x1c]	100594	1		T3	1		T33	2		T4	80
valid_sources[0x1d]	98041	1		T33	2		T4	80		T5	624
valid_sources[0x1e]	97206	1		T33	3		T4	65		T5	569
valid_sources[0x1f]	98651	1		T33	3		T4	70		T5	587
valid_sources[0x20]	96629	1		T1	1		T4	79		T108	1
valid_sources[0x21]	97465	1		T33	2		T4	95		T5	646
valid_sources[0x22]	98800	1		T33	2		T4	63		T5	599
valid_sources[0x23]	103704	1		T33	3		T4	67		T5	632
valid_sources[0x24]	96022	1		T33	119		T4	81		T5	649
valid_sources[0x25]	97826	1		T33	2		T4	75		T5	660
valid_sources[0x26]	133959	1		T33	4		T4	89		T5	614
valid_sources[0x27]	95868	1		T4	81		T5	615		T60	2
valid_sources[0x28]	96874	1		T2	1		T3	1		T31	1
valid_sources[0x29]	95811	1		T33	2		T34	10		T4	87
valid_sources[0x2a]	123626	1		T2	5		T33	13		T4	70
valid_sources[0x2b]	97183	1		T1	1		T33	1		T4	78
valid_sources[0x2c]	191622	1		T4	82		T36	1		T5	543
valid_sources[0x2d]	98497	1		T33	5		T4	75		T5	649
valid_sources[0x2e]	97786	1		T33	5		T4	80		T5	624
valid_sources[0x2f]	116382	1		T33	3		T4	85		T36	3
valid_sources[0x30]	115497	1		T3	1		T33	3		T4	100
valid_sources[0x31]	228552	1		T3	1		T4	84		T5	518
valid_sources[0x32]	97440	1		T33	3		T4	70		T5	549
valid_sources[0x33]	106856	1		T33	5		T4	90		T5	602
valid_sources[0x34]	129094	1		T33	4		T4	90		T5	572
valid_sources[0x35]	113117	1		T30	246		T4	81		T5	630
valid_sources[0x36]	97741	1		T33	3		T4	86		T5	534
valid_sources[0x37]	97294	1		T33	3		T4	76		T5	595
valid_sources[0x38]	97464	1		T3	1		T33	1		T4	71
valid_sources[0x39]	115191	1		T33	2		T4	84		T5	645
valid_sources[0x3a]	97787	1		T33	7		T4	64		T5	569
valid_sources[0x3b]	260847	1		T33	3		T4	62		T5	606
valid_sources[0x3c]	274407	1		T33	3		T4	70		T5	551
valid_sources[0x3d]	97338	1		T33	1		T4	89		T5	611
valid_sources[0x3e]	241255	1		T33	2		T109	1		T4	85
valid_sources[0x3f]	98540	1		T4	64		T5	672		T110	1
valid_sources[0x40]	99141	1		T33	59		T4	85		T5	624
valid_sources[0x41]	211549	1		T2	4		T33	1		T4	96
valid_sources[0x42]	125635	1		T33	2		T4	81		T5	621
valid_sources[0x43]	95526	1		T33	2		T4	72		T5	518
valid_sources[0x44]	244054	1		T4	90		T5	616		T44	1
valid_sources[0x45]	97905	1		T31	1		T33	2		T4	96
valid_sources[0x46]	96709	1		T4	88		T5	586		T110	1
valid_sources[0x47]	330251	1		T4	72		T36	1		T5	549
valid_sources[0x48]	96723	1		T33	3		T4	78		T5	540
valid_sources[0x49]	97645	1		T4	75		T5	608		T110	2
valid_sources[0x4a]	97431	1		T33	2		T4	84		T5	548
valid_sources[0x4b]	169111	1		T33	8		T4	90		T5	573
valid_sources[0x4c]	113821	1		T33	3		T4	85		T5	530
valid_sources[0x4d]	97553	1		T33	305		T4	71		T5	602
valid_sources[0x4e]	98115	1		T1	1		T4	72		T108	1
valid_sources[0x4f]	98339	1		T1	1		T4	62		T5	553
valid_sources[0x50]	97032	1		T33	2		T4	75		T5	549
valid_sources[0x51]	190908	1		T1	1		T33	2		T35	1
valid_sources[0x52]	96890	1		T4	69		T5	489		T110	2
valid_sources[0x53]	98244	1		T33	3		T4	85		T5	566
valid_sources[0x54]	241767	1		T4	90		T5	639		T60	2
valid_sources[0x55]	96001	1		T4	83		T5	514		T44	1
valid_sources[0x56]	96574	1		T33	2		T4	87		T5	509
valid_sources[0x57]	98318	1		T33	1		T35	2		T4	75
valid_sources[0x58]	119290	1		T2	4		T4	69		T5	556
valid_sources[0x59]	96318	1		T33	1		T4	86		T5	559
valid_sources[0x5a]	97451	1		T33	2		T4	81		T5	589
valid_sources[0x5b]	139821	1		T2	3		T33	34		T4	90
valid_sources[0x5c]	154178	1		T3	2		T4	90		T5	555
valid_sources[0x5d]	97076	1		T33	1		T4	77		T5	553
valid_sources[0x5e]	99144	1		T1	1		T4	82		T5	562
valid_sources[0x5f]	188180	1		T4	85		T5	553		T110	2
valid_sources[0x60]	124649	1		T33	3		T4	79		T5	638
valid_sources[0x61]	98712	1		T33	23		T4	76		T5	589
valid_sources[0x62]	242264	1		T1	2		T33	1		T4	80
valid_sources[0x63]	98687	1		T33	1		T4	59		T5	628
valid_sources[0x64]	120757	1		T3	1		T33	1		T4	77
valid_sources[0x65]	97374	1		T4	81		T5	574		T111	1
valid_sources[0x66]	96660	1		T33	5		T4	64		T36	1
valid_sources[0x67]	99102	1		T1	1		T33	2		T4	78
valid_sources[0x68]	147895	1		T31	1		T33	1		T4	72
valid_sources[0x69]	97301	1		T33	4		T4	97		T5	522
valid_sources[0x6a]	98542	1		T33	5		T4	85		T5	581
valid_sources[0x6b]	97349	1		T33	68		T4	95		T5	599
valid_sources[0x6c]	137424	1		T4	84		T5	635		T330	1
valid_sources[0x6d]	96821	1		T2	1		T33	6		T4	93
valid_sources[0x6e]	139845	1		T3	1		T33	1		T4	88
valid_sources[0x6f]	96934	1		T33	183		T4	69		T108	1
valid_sources[0x70]	97639	1		T4	87		T5	623		T115	442
valid_sources[0x71]	96811	1		T1	1		T33	2		T4	95
valid_sources[0x72]	148216	1		T33	5		T4	85		T5	572
valid_sources[0x73]	265463	1		T33	2		T4	90		T5	621
valid_sources[0x74]	96613	1		T1	1		T33	3		T4	94
valid_sources[0x75]	138947	1		T33	139		T4	89		T5	558
valid_sources[0x76]	165957	1		T3	1		T31	1		T56	11
valid_sources[0x77]	116035	1		T33	1		T4	84		T5	570
valid_sources[0x78]	96989	1		T4	108		T5	614		T110	1
valid_sources[0x79]	162247	1		T33	2		T109	1		T4	79
valid_sources[0x7a]	97095	1		T33	217		T35	1		T4	65
valid_sources[0x7b]	186713	1		T3	1		T33	2		T4	68
valid_sources[0x7c]	97190	1		T3	2		T4	86		T5	552
valid_sources[0x7d]	96834	1		T4	72		T5	629		T60	4
valid_sources[0x7e]	281507	1		T33	3		T76	10		T4	63
valid_sources[0x7f]	245533	1		T33	74		T4	78		T5	589
valid_sources[0x80]	96227	1		T4	64		T36	7		T5	554

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16604597

1

T1

2

T2

2

T3

18

values[0x0]

all_enables

biggest_size

273144

1

T1

3

T2

5

T3

3

values[0x1]

all_enables

biggest_size

257616

1

T1

3

T2

2

T3

2