Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16328054	1		T1	8		T2	17		T3	5
full_word	17136340	1		T1	8		T2	9		T3	23

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33464114	1		T1	16		T2	26		T3	28
auto[TlIntgErrCmd]	88	1		T213	8		T240	2		T236	7
auto[TlIntgErrData]	101	1		T213	5		T240	4		T236	6
auto[TlIntgErrBoth]	91	1		T213	7		T240	4		T236	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32790718	1		T1	5		T2	10		T3	21
auto[1]	673676	1		T1	11		T2	16		T3	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16185812	1		T1	3		T2	8		T3	3
auto[TlIntgErrNone]	partial	auto[1]	141982	1		T1	5		T2	9		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	16604784	1		T1	2		T2	2		T3	18
auto[TlIntgErrNone]	full_word	auto[1]	531536	1		T1	6		T2	7		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T213	4		T236	3		T253	4
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T213	3		T240	2		T236	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T213	1		T253	1		T257	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T252	1		T322	1		T323	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T213	2		T240	3		T236	1
auto[TlIntgErrData]	partial	auto[1]	54	1		T213	3		T240	1		T236	4
auto[TlIntgErrData]	full_word	auto[0]	6	1		T236	1		T253	1		T256	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T324	1		T325	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T213	5		T236	3		T252	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T213	2		T240	3		T236	4
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T240	1		T326	1		-	-