Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	529912719	12153	0	0
ep_in_enable_rd_A	529912719	3000	0	0
ep_out_enable_rd_A	529912719	3168	0	0
in_iso_rd_A	529912719	3168	0	0
intr_enable_rd_A	529912719	4352	0	0
out_iso_rd_A	529912719	3087	0	0
phy_config_rd_A	529912719	1609	0	0
phy_pins_drive_rd_A	529912719	2365	0	0
rxenable_setup_rd_A	529912719	3272	0	0
set_nak_out_rd_A	529912719	2662	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	12153	0	0
T211	4026	13	0	0
T212	3917	393	0	0
T213	44790	5	0	0
T235	11494	386	0	0
T236	90999	1	0	0
T240	18753	3	0	0
T241	7623	23	0	0
T252	22537	1	0	0
T253	45562	6	0	0
T295	27696	2	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	3000	0	0
T240	18753	328	0	0
T251	3812	77	0	0
T253	45562	488	0	0
T255	4904	53	0	0
T256	29712	154	0	0
T274	4277	6	0	0
T288	5156	6	0	0
T296	11936	55	0	0
T297	13682	31	0	0
T298	5184	28	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	3168	0	0
T240	18753	287	0	0
T251	3812	34	0	0
T253	45562	454	0	0
T255	4904	7	0	0
T256	29712	73	0	0
T274	4277	7	0	0
T288	5156	7	0	0
T289	4473	14	0	0
T296	11936	72	0	0
T297	13682	59	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	3168	0	0
T240	18753	167	0	0
T242	11856	4	0	0
T251	3812	19	0	0
T253	45562	625	0	0
T256	29712	129	0	0
T274	4277	98	0	0
T288	5156	18	0	0
T289	4473	27	0	0
T296	11936	86	0	0
T297	13682	15	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	4352	0	0
T240	18753	346	0	0
T251	3812	63	0	0
T253	45562	766	0	0
T256	29712	155	0	0
T274	4277	131	0	0
T288	5156	4	0	0
T289	4473	4	0	0
T296	11936	49	0	0
T297	13682	16	0	0
T299	2013	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	3087	0	0
T240	18753	132	0	0
T251	3812	44	0	0
T253	45562	550	0	0
T255	4904	47	0	0
T256	29712	165	0	0
T274	4277	105	0	0
T288	5156	14	0	0
T289	4473	38	0	0
T296	11936	27	0	0
T297	13682	65	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	1609	0	0
T240	18753	95	0	0
T251	3812	18	0	0
T253	45562	265	0	0
T255	4904	5	0	0
T256	29712	104	0	0
T274	4277	7	0	0
T289	4473	17	0	0
T296	11936	38	0	0
T297	13682	75	0	0
T298	5184	11	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	2365	0	0
T240	18753	259	0	0
T251	3812	7	0	0
T253	45562	343	0	0
T255	4904	15	0	0
T256	29712	96	0	0
T274	4277	43	0	0
T296	11936	56	0	0
T297	13682	26	0	0
T298	5184	1	0	0
T300	4966	8	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	3272	0	0
T240	18753	178	0	0
T251	3812	9	0	0
T253	45562	640	0	0
T255	4904	46	0	0
T256	29712	132	0	0
T274	4277	94	0	0
T288	5156	27	0	0
T289	4473	25	0	0
T296	11936	24	0	0
T297	13682	57	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529912719	2662	0	0
T240	18753	135	0	0
T242	11856	4	0	0
T251	3812	10	0	0
T253	45562	571	0	0
T255	4904	12	0	0
T256	29712	138	0	0
T274	4277	43	0	0
T289	4473	5	0	0
T296	11936	57	0	0
T297	13682	56	0	0