Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16010018	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16834735	1		T1	24429		T2	5		T3	8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32185339	1		T1	48425		T2	2		T3	39
values[0x0]	329390	1		T1	158		T2	4		T27	3
values[0x1]	330024	1		T1	150		T2	6		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12764351	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20080402	1		T1	29300		T2	8		T3	18

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	122430	1		T1	174		T4	909		T5	747
valid_sources[0x01]	102551	1		T1	175		T4	865		T35	1
valid_sources[0x02]	99972	1		T1	187		T4	858		T33	2
valid_sources[0x03]	102959	1		T1	187		T4	802		T5	757
valid_sources[0x04]	103563	1		T1	184		T4	845		T5	691
valid_sources[0x05]	102334	1		T1	199		T2	2		T4	871
valid_sources[0x06]	100483	1		T1	182		T27	1		T4	854
valid_sources[0x07]	100032	1		T1	183		T3	3		T4	845
valid_sources[0x08]	101535	1		T1	209		T4	855		T5	797
valid_sources[0x09]	189643	1		T1	183		T4	839		T5	647
valid_sources[0x0a]	130798	1		T1	192		T4	889		T5	627
valid_sources[0x0b]	101634	1		T1	186		T4	838		T5	795
valid_sources[0x0c]	100118	1		T1	215		T2	1		T31	1
valid_sources[0x0d]	122771	1		T1	186		T3	1		T4	832
valid_sources[0x0e]	101217	1		T1	186		T4	866		T33	1
valid_sources[0x0f]	268847	1		T1	212		T4	775		T5	716
valid_sources[0x10]	196301	1		T1	195		T4	885		T5	785
valid_sources[0x11]	145347	1		T1	189		T4	895		T5	871
valid_sources[0x12]	139181	1		T1	196		T3	1		T4	843
valid_sources[0x13]	102065	1		T1	192		T4	877		T5	496
valid_sources[0x14]	181360	1		T1	186		T4	867		T5	692
valid_sources[0x15]	101892	1		T1	186		T4	847		T5	669
valid_sources[0x16]	101694	1		T1	201		T4	903		T5	926
valid_sources[0x17]	101373	1		T1	199		T4	854		T5	714
valid_sources[0x18]	100223	1		T1	176		T3	1		T4	847
valid_sources[0x19]	102980	1		T1	204		T4	813		T5	759
valid_sources[0x1a]	179198	1		T1	194		T4	905		T33	1
valid_sources[0x1b]	103523	1		T1	176		T4	901		T33	1
valid_sources[0x1c]	101529	1		T1	205		T4	865		T5	608
valid_sources[0x1d]	281266	1		T1	208		T3	2		T4	792
valid_sources[0x1e]	102993	1		T1	201		T4	821		T35	1
valid_sources[0x1f]	101944	1		T1	203		T4	862		T24	1
valid_sources[0x20]	126880	1		T1	197		T4	854		T5	609
valid_sources[0x21]	102862	1		T1	200		T4	862		T5	747
valid_sources[0x22]	101755	1		T1	181		T4	840		T5	812
valid_sources[0x23]	101129	1		T1	194		T4	849		T33	3
valid_sources[0x24]	100712	1		T1	201		T3	2		T4	850
valid_sources[0x25]	229312	1		T1	164		T4	792		T5	570
valid_sources[0x26]	100966	1		T1	207		T4	879		T33	2
valid_sources[0x27]	102294	1		T1	199		T4	898		T35	1
valid_sources[0x28]	120502	1		T1	188		T4	838		T33	1
valid_sources[0x29]	102614	1		T1	184		T4	880		T5	643
valid_sources[0x2a]	101468	1		T1	198		T4	799		T5	727
valid_sources[0x2b]	116372	1		T1	178		T4	845		T33	2
valid_sources[0x2c]	108958	1		T1	192		T4	851		T5	575
valid_sources[0x2d]	371245	1		T1	197		T4	869		T33	1
valid_sources[0x2e]	101034	1		T1	178		T4	876		T33	1
valid_sources[0x2f]	101517	1		T1	175		T4	856		T5	892
valid_sources[0x30]	102124	1		T1	209		T4	890		T33	2
valid_sources[0x31]	102249	1		T1	173		T4	864		T35	2
valid_sources[0x32]	145830	1		T1	180		T4	792		T5	824
valid_sources[0x33]	101818	1		T1	173		T4	842		T33	3
valid_sources[0x34]	102473	1		T1	159		T3	1		T4	898
valid_sources[0x35]	251928	1		T1	203		T27	1		T4	873
valid_sources[0x36]	101532	1		T1	185		T4	898		T33	3
valid_sources[0x37]	128563	1		T1	184		T3	1		T4	859
valid_sources[0x38]	213950	1		T1	193		T4	837		T5	629
valid_sources[0x39]	129399	1		T1	191		T4	875		T5	668
valid_sources[0x3a]	140981	1		T1	185		T3	2		T4	859
valid_sources[0x3b]	306857	1		T1	191		T4	831		T35	1
valid_sources[0x3c]	102567	1		T1	187		T4	862		T5	760
valid_sources[0x3d]	136327	1		T1	179		T31	1		T4	881
valid_sources[0x3e]	103010	1		T1	192		T4	874		T33	2
valid_sources[0x3f]	129301	1		T1	190		T4	857		T32	1
valid_sources[0x40]	162737	1		T1	185		T4	873		T5	523
valid_sources[0x41]	102063	1		T1	197		T2	1		T4	800
valid_sources[0x42]	102603	1		T1	218		T4	800		T33	1
valid_sources[0x43]	101815	1		T1	189		T4	832		T5	592
valid_sources[0x44]	102928	1		T1	207		T4	769		T5	803
valid_sources[0x45]	101111	1		T1	202		T4	860		T5	724
valid_sources[0x46]	102643	1		T1	178		T4	878		T35	2
valid_sources[0x47]	151059	1		T1	203		T4	878		T33	4
valid_sources[0x48]	100493	1		T1	215		T4	849		T33	1
valid_sources[0x49]	103785	1		T1	184		T4	923		T33	1
valid_sources[0x4a]	101593	1		T1	180		T4	828		T33	1
valid_sources[0x4b]	99571	1		T1	179		T3	1		T4	832
valid_sources[0x4c]	99809	1		T1	209		T3	2		T4	862
valid_sources[0x4d]	103339	1		T1	175		T2	1		T29	16
valid_sources[0x4e]	134978	1		T1	193		T4	857		T33	1
valid_sources[0x4f]	126745	1		T1	172		T3	3		T4	856
valid_sources[0x50]	100444	1		T1	193		T4	874		T33	2
valid_sources[0x51]	103764	1		T1	202		T4	863		T5	735
valid_sources[0x52]	141363	1		T1	194		T4	868		T33	2
valid_sources[0x53]	100491	1		T1	182		T3	1		T4	850
valid_sources[0x54]	100760	1		T1	189		T4	841		T33	1
valid_sources[0x55]	100673	1		T1	158		T3	1		T4	855
valid_sources[0x56]	210418	1		T1	194		T4	904		T5	682
valid_sources[0x57]	151730	1		T1	172		T4	848		T32	1
valid_sources[0x58]	100175	1		T1	189		T27	1		T4	841
valid_sources[0x59]	161362	1		T1	186		T4	870		T33	2
valid_sources[0x5a]	102863	1		T1	156		T4	879		T32	1
valid_sources[0x5b]	132226	1		T1	197		T4	843		T5	597
valid_sources[0x5c]	101697	1		T1	196		T4	867		T5	775
valid_sources[0x5d]	101224	1		T1	185		T3	1		T4	904
valid_sources[0x5e]	111727	1		T1	183		T4	833		T33	1
valid_sources[0x5f]	100617	1		T1	177		T4	809		T33	2
valid_sources[0x60]	102235	1		T1	203		T3	2		T4	913
valid_sources[0x61]	103555	1		T1	195		T4	829		T5	677
valid_sources[0x62]	139218	1		T1	196		T4	848		T5	657
valid_sources[0x63]	100331	1		T1	198		T4	853		T5	695
valid_sources[0x64]	131124	1		T1	182		T4	901		T5	730
valid_sources[0x65]	127448	1		T1	166		T4	840		T5	674
valid_sources[0x66]	102782	1		T1	202		T4	852		T33	1
valid_sources[0x67]	101908	1		T1	192		T4	899		T5	636
valid_sources[0x68]	220750	1		T1	205		T4	827		T33	13
valid_sources[0x69]	199265	1		T1	190		T4	842		T5	691
valid_sources[0x6a]	101141	1		T1	192		T4	873		T5	738
valid_sources[0x6b]	118931	1		T1	204		T4	870		T5	676
valid_sources[0x6c]	117575	1		T1	181		T2	2		T3	1
valid_sources[0x6d]	102130	1		T1	222		T4	880		T5	710
valid_sources[0x6e]	101591	1		T1	189		T4	862		T5	740
valid_sources[0x6f]	100566	1		T1	159		T30	27		T4	773
valid_sources[0x70]	102675	1		T1	192		T4	871		T5	722
valid_sources[0x71]	106311	1		T1	171		T4	802		T41	10
valid_sources[0x72]	131863	1		T1	184		T4	866		T5	658
valid_sources[0x73]	124483	1		T1	203		T2	2		T4	913
valid_sources[0x74]	102826	1		T1	195		T3	1		T4	843
valid_sources[0x75]	102945	1		T1	185		T4	879		T33	1
valid_sources[0x76]	100265	1		T1	205		T4	850		T35	1
valid_sources[0x77]	101124	1		T1	179		T4	838		T33	5
valid_sources[0x78]	116511	1		T1	204		T4	787		T5	789
valid_sources[0x79]	101603	1		T1	192		T4	859		T5	676
valid_sources[0x7a]	102140	1		T1	209		T31	3		T4	872
valid_sources[0x7b]	491158	1		T1	211		T3	4		T4	847
valid_sources[0x7c]	101115	1		T1	175		T4	894		T35	1
valid_sources[0x7d]	100538	1		T1	203		T4	863		T5	555
valid_sources[0x7e]	202647	1		T1	197		T4	872		T5	652
valid_sources[0x7f]	101529	1		T1	187		T4	816		T5	575
valid_sources[0x80]	103476	1		T1	171		T4	867		T5	614

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16303619

1

T1

24209

T2

2

T3

1

values[0x0]

all_enables

biggest_size

273374

1

T1

116

T2

1

T27

3

values[0x1]

all_enables

biggest_size

257742

1

T1

104

T2

2

T3

7