Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16024467	1		T1	24304		T2	7		T3	47
full_word	16835765	1		T1	24429		T2	5		T3	8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32859932	1		T1	48733		T2	12		T3	55
auto[TlIntgErrCmd]	113	1		T210	7		T211	7		T212	7
auto[TlIntgErrData]	100	1		T210	7		T211	4		T212	9
auto[TlIntgErrBoth]	87	1		T210	6		T211	9		T212	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32187247	1		T1	48425		T2	2		T3	39
auto[1]	672985	1		T1	308		T2	10		T3	16

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15883310	1		T1	24216		T3	38		T27	3
auto[TlIntgErrNone]	partial	auto[1]	140878	1		T1	88		T2	7		T3	9
auto[TlIntgErrNone]	full_word	auto[0]	16303811	1		T1	24209		T2	2		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	531933	1		T1	220		T2	3		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T211	2		T212	4		T229	2
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T210	7		T211	3		T212	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T211	2		T212	1		T229	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T293	1		T291	1		T294	2
auto[TlIntgErrData]	partial	auto[0]	42	1		T210	4		T211	3		T212	4
auto[TlIntgErrData]	partial	auto[1]	54	1		T210	2		T211	1		T212	5
auto[TlIntgErrData]	full_word	auto[0]	1	1		T295	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T210	1		T263	1		T292	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T210	2		T211	2		T212	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T210	4		T211	6		T212	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T211	1		T293	1		T296	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T212	1		T229	1		T297	1