Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	525977569	12184	0	0
ep_in_enable_rd_A	525977569	3482	0	0
ep_out_enable_rd_A	525977569	3434	0	0
in_iso_rd_A	525977569	3138	0	0
intr_enable_rd_A	525977569	4932	0	0
out_iso_rd_A	525977569	3116	0	0
phy_config_rd_A	525977569	2307	0	0
phy_pins_drive_rd_A	525977569	2737	0	0
rxenable_setup_rd_A	525977569	3370	0	0
set_nak_out_rd_A	525977569	3402	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	12184	0	0
T188	4298	20	0	0
T189	4252	7	0	0
T190	4883	7	0	0
T210	48235	2	0	0
T211	35572	10	0	0
T212	38699	4	0	0
T219	3472	23	0	0
T220	9248	467	0	0
T221	16660	905	0	0
T229	42724	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3482	0	0
T190	4883	44	0	0
T223	8479	117	0	0
T229	42724	281	0	0
T230	24283	245	0	0
T240	4688	74	0	0
T254	12079	47	0	0
T257	2938	14	0	0
T261	5796	8	0	0
T262	3645	5	0	0
T263	22176	401	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3434	0	0
T190	4883	12	0	0
T223	8479	14	0	0
T229	42724	202	0	0
T230	24283	301	0	0
T240	4688	27	0	0
T254	12079	23	0	0
T257	2938	1	0	0
T261	5796	28	0	0
T263	22176	277	0	0
T264	19049	175	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3138	0	0
T190	4883	8	0	0
T221	16660	5	0	0
T223	8479	41	0	0
T229	42724	344	0	0
T230	24283	247	0	0
T254	12079	43	0	0
T261	5796	6	0	0
T262	3645	1	0	0
T263	22176	295	0	0
T264	19049	216	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	4932	0	0
T190	4883	97	0	0
T197	1810	17	0	0
T223	8479	87	0	0
T229	42724	326	0	0
T230	24283	152	0	0
T240	4688	42	0	0
T254	12079	22	0	0
T257	2938	24	0	0
T265	2597	10	0	0
T266	2184	16	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3116	0	0
T190	4883	45	0	0
T223	8479	55	0	0
T229	42724	303	0	0
T230	24283	232	0	0
T240	4688	40	0	0
T254	12079	58	0	0
T262	3645	9	0	0
T263	22176	150	0	0
T264	19049	236	0	0
T267	41938	229	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	2307	0	0
T190	4883	47	0	0
T221	16660	2	0	0
T223	8479	17	0	0
T229	42724	170	0	0
T230	24283	97	0	0
T254	12079	36	0	0
T261	5796	28	0	0
T262	3645	9	0	0
T263	22176	166	0	0
T264	19049	104	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	2737	0	0
T190	4883	5	0	0
T223	8479	43	0	0
T229	42724	191	0	0
T230	24283	210	0	0
T240	4688	18	0	0
T254	12079	40	0	0
T257	2938	18	0	0
T261	5796	11	0	0
T262	3645	2	0	0
T263	22176	199	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3370	0	0
T190	4883	12	0	0
T221	16660	13	0	0
T223	8479	106	0	0
T229	42724	329	0	0
T230	24283	199	0	0
T240	4688	24	0	0
T254	12079	18	0	0
T257	2938	21	0	0
T261	5796	9	0	0
T262	3645	3	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525977569	3402	0	0
T190	4883	1	0	0
T223	8479	18	0	0
T229	42724	305	0	0
T230	24283	345	0	0
T240	4688	30	0	0
T254	12079	31	0	0
T257	2938	1	0	0
T261	5796	45	0	0
T262	3645	8	0	0
T263	22176	227	0	0