Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16352414	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17135559	1		T1	6		T2	16		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32851259	1		T1	2		T2	70		T3	4
values[0x0]	318357	1		T1	5		T2	8		T3	7
values[0x1]	318357	1		T1	4		T2	11		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13038266	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20449707	1		T1	8		T2	45		T3	9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	99848	1		T3	1		T18	1		T4	28
valid_sources[0x01]	207031	1		T4	98		T5	139		T6	494
valid_sources[0x02]	100499	1		T4	65		T20	3		T5	101
valid_sources[0x03]	102514	1		T16	3		T4	107		T20	4
valid_sources[0x04]	117454	1		T4	124		T5	136		T6	456
valid_sources[0x05]	101852	1		T4	16		T5	93		T6	458
valid_sources[0x06]	122737	1		T4	91		T19	2		T20	2
valid_sources[0x07]	313629	1		T4	191		T20	1		T5	125
valid_sources[0x08]	104062	1		T4	90		T20	1		T5	129
valid_sources[0x09]	103291	1		T16	2		T18	37		T4	113
valid_sources[0x0a]	240159	1		T4	158		T5	115		T6	491
valid_sources[0x0b]	219840	1		T4	326		T20	2		T27	1
valid_sources[0x0c]	103054	1		T3	1		T18	2		T4	147
valid_sources[0x0d]	101497	1		T4	49		T20	2		T5	139
valid_sources[0x0e]	126235	1		T16	3		T18	18		T4	18
valid_sources[0x0f]	105025	1		T4	101		T5	143		T6	539
valid_sources[0x10]	186111	1		T18	2		T4	13		T20	1
valid_sources[0x11]	101713	1		T16	2		T4	92		T5	107
valid_sources[0x12]	101915	1		T4	23		T20	3		T5	130
valid_sources[0x13]	103927	1		T4	172		T20	3		T5	125
valid_sources[0x14]	100618	1		T4	56		T20	1		T5	109
valid_sources[0x15]	102346	1		T4	85		T20	2		T5	120
valid_sources[0x16]	103167	1		T4	135		T20	4		T5	138
valid_sources[0x17]	201935	1		T4	62		T20	2		T5	134
valid_sources[0x18]	101059	1		T4	89		T20	2		T5	104
valid_sources[0x19]	333499	1		T4	9		T5	118		T6	413
valid_sources[0x1a]	100994	1		T4	145		T5	119		T6	472
valid_sources[0x1b]	102264	1		T4	10		T20	2		T5	131
valid_sources[0x1c]	103638	1		T18	9		T4	117		T20	1
valid_sources[0x1d]	200955	1		T4	112		T5	143		T6	366
valid_sources[0x1e]	192658	1		T18	32		T4	69		T5	105
valid_sources[0x1f]	102281	1		T4	94		T5	125		T6	479
valid_sources[0x20]	102822	1		T4	29		T5	104		T6	477
valid_sources[0x21]	101225	1		T4	142		T5	134		T6	575
valid_sources[0x22]	101993	1		T4	138		T20	4		T5	118
valid_sources[0x23]	101017	1		T16	1		T17	1		T4	44
valid_sources[0x24]	120088	1		T4	86		T20	1		T5	123
valid_sources[0x25]	102413	1		T4	14		T5	134		T6	560
valid_sources[0x26]	102751	1		T4	131		T20	1		T5	113
valid_sources[0x27]	129842	1		T4	91		T27	1		T5	105
valid_sources[0x28]	278677	1		T4	144		T20	1		T5	107
valid_sources[0x29]	101464	1		T4	104		T5	138		T6	450
valid_sources[0x2a]	103043	1		T3	1		T4	44		T20	2
valid_sources[0x2b]	101806	1		T4	116		T20	1		T5	141
valid_sources[0x2c]	118167	1		T4	131		T5	115		T6	501
valid_sources[0x2d]	104502	1		T4	59		T27	1		T5	107
valid_sources[0x2e]	101935	1		T18	8		T4	41		T20	2
valid_sources[0x2f]	103270	1		T4	90		T5	128		T6	546
valid_sources[0x30]	100566	1		T4	59		T5	110		T6	558
valid_sources[0x31]	100709	1		T4	14		T20	1		T5	129
valid_sources[0x32]	99937	1		T18	12		T4	38		T20	1
valid_sources[0x33]	102539	1		T1	1		T4	113		T20	1
valid_sources[0x34]	205751	1		T18	17		T4	11		T20	1
valid_sources[0x35]	102868	1		T18	12		T4	23		T20	2
valid_sources[0x36]	100635	1		T4	124		T20	1		T5	128
valid_sources[0x37]	100805	1		T1	3		T3	1		T18	1
valid_sources[0x38]	117237	1		T4	229		T20	5		T5	121
valid_sources[0x39]	134247	1		T4	89		T5	115		T6	567
valid_sources[0x3a]	101677	1		T4	19		T5	134		T6	367
valid_sources[0x3b]	102679	1		T4	30		T5	127		T6	477
valid_sources[0x3c]	104507	1		T4	89		T20	2		T5	102
valid_sources[0x3d]	124295	1		T4	115		T27	1		T5	118
valid_sources[0x3e]	128058	1		T4	82		T5	115		T28	44
valid_sources[0x3f]	214724	1		T4	92		T20	1		T5	115
valid_sources[0x40]	118852	1		T4	56		T20	1		T5	141
valid_sources[0x41]	221730	1		T4	116		T20	3		T5	116
valid_sources[0x42]	101832	1		T4	97		T5	149		T6	376
valid_sources[0x43]	128728	1		T18	19		T4	108		T20	2
valid_sources[0x44]	102396	1		T4	105		T20	1		T5	106
valid_sources[0x45]	102226	1		T4	57		T5	126		T6	740
valid_sources[0x46]	101328	1		T4	14		T5	113		T6	345
valid_sources[0x47]	309276	1		T3	1		T4	38		T20	3
valid_sources[0x48]	99580	1		T4	84		T20	1		T5	109
valid_sources[0x49]	101276	1		T4	48		T20	2		T5	97
valid_sources[0x4a]	99560	1		T4	158		T20	2		T5	106
valid_sources[0x4b]	211368	1		T4	83		T20	3		T5	78
valid_sources[0x4c]	115899	1		T4	55		T20	2		T5	107
valid_sources[0x4d]	100798	1		T17	1		T18	38		T4	166
valid_sources[0x4e]	259328	1		T4	89		T5	135		T6	580
valid_sources[0x4f]	259689	1		T4	187		T20	2		T5	117
valid_sources[0x50]	313627	1		T18	3		T4	86		T20	1
valid_sources[0x51]	100095	1		T4	108		T20	1		T5	125
valid_sources[0x52]	101489	1		T3	1		T18	118		T4	112
valid_sources[0x53]	102846	1		T4	150		T20	3		T5	122
valid_sources[0x54]	100159	1		T4	201		T5	136		T6	523
valid_sources[0x55]	99894	1		T4	104		T5	101		T6	494
valid_sources[0x56]	102483	1		T4	57		T20	2		T27	1
valid_sources[0x57]	102146	1		T4	131		T5	122		T6	485
valid_sources[0x58]	101943	1		T18	12		T4	29		T20	2
valid_sources[0x59]	210160	1		T4	116		T5	114		T6	400
valid_sources[0x5a]	169308	1		T4	49		T5	105		T6	435
valid_sources[0x5b]	133239	1		T4	69		T5	99		T6	511
valid_sources[0x5c]	102157	1		T4	157		T5	127		T6	538
valid_sources[0x5d]	103057	1		T4	113		T20	4		T5	129
valid_sources[0x5e]	100255	1		T4	35		T5	93		T103	2
valid_sources[0x5f]	140362	1		T4	49		T5	131		T6	527
valid_sources[0x60]	103231	1		T4	71		T20	2		T5	113
valid_sources[0x61]	102862	1		T4	128		T20	1		T5	128
valid_sources[0x62]	104016	1		T17	2		T4	169		T20	1
valid_sources[0x63]	103123	1		T4	88		T20	1		T5	128
valid_sources[0x64]	120531	1		T3	1		T4	50		T5	107
valid_sources[0x65]	105227	1		T4	54		T20	1		T5	123
valid_sources[0x66]	124136	1		T4	11		T20	3		T5	115
valid_sources[0x67]	101529	1		T18	12		T4	45		T5	92
valid_sources[0x68]	100221	1		T4	44		T5	113		T6	622
valid_sources[0x69]	117259	1		T18	53		T4	60		T20	1
valid_sources[0x6a]	101442	1		T4	40		T20	2		T5	88
valid_sources[0x6b]	160461	1		T4	118		T20	1		T5	114
valid_sources[0x6c]	373395	1		T4	83		T5	140		T6	657
valid_sources[0x6d]	100155	1		T4	27		T20	1		T27	1
valid_sources[0x6e]	104395	1		T4	14		T20	1		T5	86
valid_sources[0x6f]	363526	1		T4	131		T5	120		T6	543
valid_sources[0x70]	121753	1		T4	41		T20	1		T5	132
valid_sources[0x71]	101223	1		T4	35		T5	124		T6	344
valid_sources[0x72]	101928	1		T4	91		T20	1		T5	119
valid_sources[0x73]	255706	1		T4	148		T5	123		T6	426
valid_sources[0x74]	102968	1		T4	105		T20	1		T27	1
valid_sources[0x75]	101985	1		T4	26		T5	141		T6	408
valid_sources[0x76]	130156	1		T4	72		T20	1		T5	111
valid_sources[0x77]	101969	1		T4	203		T5	108		T6	394
valid_sources[0x78]	120141	1		T4	59		T20	1		T5	115
valid_sources[0x79]	223405	1		T4	36		T20	2		T5	114
valid_sources[0x7a]	162304	1		T4	88		T20	3		T5	119
valid_sources[0x7b]	101419	1		T4	87		T20	3		T5	132
valid_sources[0x7c]	102700	1		T4	62		T20	1		T5	127
valid_sources[0x7d]	100889	1		T17	3		T18	9		T4	114
valid_sources[0x7e]	100436	1		T4	61		T20	1		T5	102
valid_sources[0x7f]	101906	1		T4	38		T27	1		T5	140
valid_sources[0x80]	101536	1		T4	100		T20	4		T5	117

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16628080

1

T1

1

T2

4

T3

3

values[0x0]

all_enables

biggest_size

261815

1

T1

4

T2

6

T3

4

values[0x1]

all_enables

biggest_size

245664

1

T1

1

T2

6

T3

2