Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16368768	1		T1	5		T2	73		T3	5
full_word	17136690	1		T1	6		T2	16		T3	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33505188	1		T1	11		T2	89		T3	14
auto[TlIntgErrCmd]	90	1		T207	4		T228	5		T234	4
auto[TlIntgErrData]	95	1		T207	7		T234	11		T322	7
auto[TlIntgErrBoth]	85	1		T207	9		T228	5		T234	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32853305	1		T1	2		T2	70		T3	4
auto[1]	652153	1		T1	9		T2	19		T3	10

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16224892	1		T1	1		T2	66		T3	1
auto[TlIntgErrNone]	partial	auto[1]	143618	1		T1	4		T2	7		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	16628290	1		T1	1		T2	4		T3	3
auto[TlIntgErrNone]	full_word	auto[1]	508388	1		T1	5		T2	12		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T207	1		T228	2		T234	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1		T207	3		T228	1		T234	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T228	2		T318	1		T323	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T284	1		T324	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1		T207	4		T234	5		T322	2
auto[TlIntgErrData]	partial	auto[1]	51	1		T207	3		T234	6		T322	5
auto[TlIntgErrData]	full_word	auto[0]	2	1		T323	1		T325	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1		T326	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T207	6		T228	3		T234	1
auto[TlIntgErrBoth]	partial	auto[1]	49	1		T207	3		T228	2		T234	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T234	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T284	1		T327	1		-	-