Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	517430206	12149	0	0
ep_in_enable_rd_A	517430206	1747	0	0
ep_out_enable_rd_A	517430206	2116	0	0
in_iso_rd_A	517430206	2124	0	0
intr_enable_rd_A	517430206	3156	0	0
out_iso_rd_A	517430206	2340	0	0
phy_config_rd_A	517430206	1464	0	0
phy_pins_drive_rd_A	517430206	1781	0	0
rxenable_setup_rd_A	517430206	2279	0	0
set_nak_out_rd_A	517430206	2522	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	12149	0	0
T205	12750	726	0	0
T206	3736	9	0	0
T207	34787	4	0	0
T228	19279	4	0	0
T229	7449	11	0	0
T234	24402	4	0	0
T235	11876	771	0	0
T236	14006	869	0	0
T245	3918	10	0	0
T246	3852	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	1747	0	0
T229	7449	61	0	0
T245	3918	25	0	0
T248	6571	3	0	0
T264	3662	75	0	0
T271	5845	5	0	0
T272	8667	16	0	0
T281	3169	56	0	0
T282	34997	68	0	0
T283	6964	7	0	0
T284	20295	112	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	2116	0	0
T229	7449	57	0	0
T245	3918	30	0	0
T248	6571	55	0	0
T264	3662	32	0	0
T271	5845	14	0	0
T272	8667	57	0	0
T281	3169	62	0	0
T282	34997	110	0	0
T283	6964	6	0	0
T284	20295	105	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	2124	0	0
T229	7449	89	0	0
T242	16377	4	0	0
T248	6571	57	0	0
T264	3662	28	0	0
T271	5845	41	0	0
T272	8667	28	0	0
T281	3169	55	0	0
T282	34997	149	0	0
T283	6964	2	0	0
T284	20295	55	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	3156	0	0
T215	4084	1	0	0
T229	7449	95	0	0
T245	3918	37	0	0
T248	6571	5	0	0
T264	3662	32	0	0
T271	5845	13	0	0
T272	8667	10	0	0
T281	3169	4	0	0
T285	4323	30	0	0
T286	2565	11	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	2340	0	0
T229	7449	83	0	0
T245	3918	31	0	0
T248	6571	58	0	0
T264	3662	37	0	0
T271	5845	52	0	0
T272	8667	24	0	0
T281	3169	56	0	0
T282	34997	123	0	0
T283	6964	5	0	0
T284	20295	96	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	1464	0	0
T229	7449	15	0	0
T245	3918	3	0	0
T248	6571	1	0	0
T264	3662	17	0	0
T271	5845	35	0	0
T272	8667	20	0	0
T281	3169	1	0	0
T282	34997	56	0	0
T283	6964	6	0	0
T284	20295	103	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	1781	0	0
T205	12750	2	0	0
T229	7449	44	0	0
T245	3918	19	0	0
T248	6571	11	0	0
T264	3662	31	0	0
T271	5845	12	0	0
T272	8667	8	0	0
T281	3169	1	0	0
T282	34997	142	0	0
T283	6964	4	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	2279	0	0
T229	7449	82	0	0
T245	3918	8	0	0
T248	6571	3	0	0
T264	3662	37	0	0
T271	5845	28	0	0
T272	8667	39	0	0
T281	3169	3	0	0
T282	34997	135	0	0
T283	6964	6	0	0
T284	20295	147	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517430206	2522	0	0
T205	12750	16	0	0
T229	7449	15	0	0
T245	3918	3	0	0
T248	6571	11	0	0
T264	3662	65	0	0
T272	8667	46	0	0
T281	3169	38	0	0
T282	34997	123	0	0
T283	6964	7	0	0
T284	20295	124	0	0