Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16068145	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	16882936	1		T1	4		T2	7		T3	16

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32292592	1		T1	3		T2	2		T3	16
values[0x0]	329611	1		T1	1		T2	6		T3	7
values[0x1]	328878	1		T1	1		T2	1		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	12813042	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20138039	1		T1	4		T2	7		T3	20

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	98082	1		T4	121		T7	1		T5	612
valid_sources[0x01]	97061	1		T1	1		T4	169		T7	2
valid_sources[0x02]	97439	1		T4	116		T5	638		T20	1
valid_sources[0x03]	98174	1		T4	111		T7	2		T5	626
valid_sources[0x04]	100248	1		T27	12		T4	161		T5	681
valid_sources[0x05]	97335	1		T4	98		T5	698		T23	55
valid_sources[0x06]	260017	1		T4	134		T7	1		T5	676
valid_sources[0x07]	129147	1		T4	117		T5	683		T23	57
valid_sources[0x08]	100347	1		T4	138		T7	1		T5	729
valid_sources[0x09]	121140	1		T4	128		T5	676		T20	1
valid_sources[0x0a]	98257	1		T4	154		T7	3		T5	612
valid_sources[0x0b]	98669	1		T4	127		T7	1		T5	708
valid_sources[0x0c]	216546	1		T4	141		T7	1		T5	643
valid_sources[0x0d]	120371	1		T3	1		T4	136		T5	659
valid_sources[0x0e]	97729	1		T4	144		T5	689		T23	76
valid_sources[0x0f]	97504	1		T4	108		T7	3		T5	624
valid_sources[0x10]	97448	1		T4	119		T7	3		T5	699
valid_sources[0x11]	97752	1		T4	126		T7	1		T5	604
valid_sources[0x12]	216653	1		T4	133		T5	684		T20	1
valid_sources[0x13]	100615	1		T4	116		T7	4		T5	672
valid_sources[0x14]	98419	1		T4	110		T7	2		T5	579
valid_sources[0x15]	97594	1		T4	110		T5	632		T23	54
valid_sources[0x16]	129040	1		T4	142		T7	1		T5	642
valid_sources[0x17]	96311	1		T4	129		T17	1		T5	666
valid_sources[0x18]	99006	1		T4	138		T5	645		T23	67
valid_sources[0x19]	226920	1		T4	138		T7	2		T5	616
valid_sources[0x1a]	99176	1		T3	1		T4	125		T5	654
valid_sources[0x1b]	100320	1		T4	109		T5	623		T20	3
valid_sources[0x1c]	97256	1		T4	163		T7	2		T5	589
valid_sources[0x1d]	168290	1		T4	130		T7	2		T5	696
valid_sources[0x1e]	97810	1		T3	1		T4	152		T5	672
valid_sources[0x1f]	96321	1		T4	140		T5	652		T23	55
valid_sources[0x20]	97586	1		T4	170		T7	1		T17	9
valid_sources[0x21]	97323	1		T4	149		T7	2		T5	668
valid_sources[0x22]	233650	1		T4	138		T7	1		T5	614
valid_sources[0x23]	300958	1		T4	149		T7	1		T5	723
valid_sources[0x24]	131666	1		T4	158		T7	2		T5	632
valid_sources[0x25]	113927	1		T4	128		T7	2		T5	653
valid_sources[0x26]	97998	1		T4	163		T17	10		T5	716
valid_sources[0x27]	116088	1		T1	1		T4	149		T17	14
valid_sources[0x28]	101318	1		T4	138		T5	610		T21	1
valid_sources[0x29]	322029	1		T4	97		T17	9		T5	758
valid_sources[0x2a]	210656	1		T4	130		T17	11		T5	662
valid_sources[0x2b]	97345	1		T3	1		T4	147		T7	1
valid_sources[0x2c]	125269	1		T4	132		T5	627		T20	1
valid_sources[0x2d]	98708	1		T4	132		T7	2		T5	637
valid_sources[0x2e]	98611	1		T3	1		T4	161		T7	3
valid_sources[0x2f]	97181	1		T4	148		T7	2		T5	621
valid_sources[0x30]	98219	1		T3	1		T4	123		T5	691
valid_sources[0x31]	97569	1		T4	113		T7	1		T5	643
valid_sources[0x32]	104170	1		T4	129		T7	2		T5	584
valid_sources[0x33]	156877	1		T4	135		T7	1		T5	743
valid_sources[0x34]	148951	1		T4	134		T7	1		T5	664
valid_sources[0x35]	102831	1		T4	145		T5	677		T23	77
valid_sources[0x36]	101793	1		T4	116		T5	689		T23	59
valid_sources[0x37]	96692	1		T4	119		T7	1		T5	675
valid_sources[0x38]	112970	1		T4	109		T7	1		T5	677
valid_sources[0x39]	96648	1		T4	128		T7	1		T5	686
valid_sources[0x3a]	97278	1		T4	126		T5	635		T20	1
valid_sources[0x3b]	98644	1		T4	126		T5	661		T23	66
valid_sources[0x3c]	118789	1		T4	117		T5	685		T22	1
valid_sources[0x3d]	97475	1		T4	137		T5	630		T23	91
valid_sources[0x3e]	110553	1		T4	121		T5	649		T23	61
valid_sources[0x3f]	98900	1		T3	1		T4	138		T7	2
valid_sources[0x40]	99404	1		T4	159		T5	712		T20	1
valid_sources[0x41]	101846	1		T4	137		T5	618		T23	59
valid_sources[0x42]	129312	1		T4	146		T7	4		T17	4
valid_sources[0x43]	101181	1		T4	147		T17	10		T5	678
valid_sources[0x44]	134578	1		T4	164		T7	1		T5	650
valid_sources[0x45]	149294	1		T4	132		T7	1		T5	614
valid_sources[0x46]	98317	1		T4	146		T7	1		T5	651
valid_sources[0x47]	118332	1		T4	151		T7	1		T5	650
valid_sources[0x48]	145560	1		T3	1		T4	146		T5	656
valid_sources[0x49]	100325	1		T3	1		T4	128		T7	1
valid_sources[0x4a]	99145	1		T4	138		T5	576		T23	83
valid_sources[0x4b]	98939	1		T4	109		T7	3		T5	629
valid_sources[0x4c]	127181	1		T4	138		T7	1		T5	684
valid_sources[0x4d]	216703	1		T4	129		T7	2		T5	590
valid_sources[0x4e]	140710	1		T4	130		T17	6		T5	653
valid_sources[0x4f]	137823	1		T4	143		T7	2		T5	674
valid_sources[0x50]	98546	1		T4	144		T7	1		T5	681
valid_sources[0x51]	272829	1		T4	135		T7	1		T5	658
valid_sources[0x52]	100187	1		T4	112		T7	1		T5	621
valid_sources[0x53]	97917	1		T4	110		T5	671		T23	61
valid_sources[0x54]	99599	1		T4	115		T5	716		T20	1
valid_sources[0x55]	127326	1		T3	1		T4	130		T7	1
valid_sources[0x56]	161877	1		T4	149		T5	644		T23	72
valid_sources[0x57]	142935	1		T4	150		T7	1		T5	630
valid_sources[0x58]	97240	1		T4	138		T7	1		T5	621
valid_sources[0x59]	96659	1		T4	126		T7	2		T5	672
valid_sources[0x5a]	127669	1		T4	137		T7	1		T17	11
valid_sources[0x5b]	99035	1		T4	127		T5	701		T20	3
valid_sources[0x5c]	98359	1		T3	1		T4	140		T7	1
valid_sources[0x5d]	118499	1		T4	136		T7	2		T5	615
valid_sources[0x5e]	99940	1		T4	134		T7	1		T5	677
valid_sources[0x5f]	98650	1		T4	140		T7	1		T17	3
valid_sources[0x60]	402569	1		T28	1		T4	158		T5	660
valid_sources[0x61]	121950	1		T4	146		T7	2		T5	657
valid_sources[0x62]	98406	1		T4	127		T7	1		T5	632
valid_sources[0x63]	114388	1		T4	130		T5	674		T22	1
valid_sources[0x64]	98108	1		T4	142		T5	687		T20	1
valid_sources[0x65]	100864	1		T4	120		T7	2		T5	654
valid_sources[0x66]	97584	1		T4	116		T17	9		T5	676
valid_sources[0x67]	97139	1		T4	138		T7	1		T17	9
valid_sources[0x68]	98742	1		T4	140		T5	637		T23	69
valid_sources[0x69]	139198	1		T4	142		T5	665		T23	66
valid_sources[0x6a]	98407	1		T4	139		T7	1		T5	685
valid_sources[0x6b]	135001	1		T2	4		T28	1		T4	128
valid_sources[0x6c]	97344	1		T4	135		T7	2		T5	648
valid_sources[0x6d]	156558	1		T4	137		T7	2		T5	631
valid_sources[0x6e]	100154	1		T28	3		T4	134		T5	673
valid_sources[0x6f]	143116	1		T4	148		T5	645		T23	89
valid_sources[0x70]	370442	1		T4	154		T7	1		T5	664
valid_sources[0x71]	97315	1		T4	148		T5	677		T20	1
valid_sources[0x72]	99556	1		T4	138		T5	709		T20	1
valid_sources[0x73]	210272	1		T4	134		T5	673		T23	67
valid_sources[0x74]	99041	1		T4	144		T7	1		T17	40
valid_sources[0x75]	98176	1		T4	142		T5	706		T23	68
valid_sources[0x76]	98173	1		T4	136		T7	1		T5	639
valid_sources[0x77]	97619	1		T4	142		T5	694		T23	77
valid_sources[0x78]	178463	1		T4	128		T5	699		T23	56
valid_sources[0x79]	97467	1		T4	125		T5	649		T20	2
valid_sources[0x7a]	97138	1		T1	1		T4	147		T7	1
valid_sources[0x7b]	96834	1		T28	3		T4	129		T7	1
valid_sources[0x7c]	97334	1		T4	147		T5	598		T23	48
valid_sources[0x7d]	97685	1		T4	135		T7	1		T5	653
valid_sources[0x7e]	169192	1		T4	130		T17	6		T5	673
valid_sources[0x7f]	98831	1		T4	145		T7	1		T5	690
valid_sources[0x80]	99158	1		T4	119		T5	662		T23	63

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16352879

1

T1

2

T3

11

T27

2

values[0x0]

all_enables

biggest_size

273644

1

T1

1

T2

6

T3

5

values[0x1]

all_enables

biggest_size

256413

1

T1

1

T2

1

T28

1