Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16081232	1		T1	1		T2	2		T3	11
full_word	16883866	1		T1	4		T2	7		T3	16

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32964808	1		T1	5		T2	9		T3	27
auto[TlIntgErrCmd]	100	1		T190	3		T191	8		T212	2
auto[TlIntgErrData]	104	1		T190	4		T191	8		T212	6
auto[TlIntgErrBoth]	86	1		T190	3		T191	4		T212	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32294336	1		T1	3		T2	2		T3	16
auto[1]	670762	1		T1	2		T2	7		T3	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15941164	1		T1	1		T2	2		T3	5
auto[TlIntgErrNone]	partial	auto[1]	139799	1		T3	6		T27	5		T28	4
auto[TlIntgErrNone]	full_word	auto[0]	16353038	1		T1	2		T3	11		T27	2
auto[TlIntgErrNone]	full_word	auto[1]	530807	1		T1	2		T2	7		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T190	3		T191	1		T212	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T191	6		T209	1		T229	4
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T191	1		T232	1		T283	1
auto[TlIntgErrData]	partial	auto[0]	47	1		T190	3		T191	4		T212	2
auto[TlIntgErrData]	partial	auto[1]	48	1		T190	1		T191	3		T212	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T191	1		T212	1		T284	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T229	1		T230	1		T285	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T190	2		T191	2		T209	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T190	1		T191	2		T212	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T229	2		T232	1		T286	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T209	1		T229	1		T287	1