Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	523833492	11389	0	0
ep_in_enable_rd_A	523833492	3768	0	0
ep_out_enable_rd_A	523833492	3744	0	0
in_iso_rd_A	523833492	3617	0	0
intr_enable_rd_A	523833492	4700	0	0
out_iso_rd_A	523833492	3651	0	0
phy_config_rd_A	523833492	2243	0	0
phy_pins_drive_rd_A	523833492	3161	0	0
rxenable_setup_rd_A	523833492	4086	0	0
set_nak_out_rd_A	523833492	3714	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	11389	0	0
T190	23292	5	0	0
T191	34938	8	0	0
T192	8884	25	0	0
T209	16659	2	0	0
T210	15107	746	0	0
T211	6925	36	0	0
T212	14203	2	0	0
T229	106571	5	0	0
T230	21334	2	0	0
T231	6337	4	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3768	0	0
T190	23292	216	0	0
T192	8884	100	0	0
T231	6337	1	0	0
T232	24033	165	0	0
T242	3516	41	0	0
T243	4676	67	0	0
T245	43687	215	0	0
T254	9441	51	0	0
T257	10306	56	0	0
T258	9910	68	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3744	0	0
T190	23292	180	0	0
T192	8884	48	0	0
T231	6337	4	0	0
T232	24033	342	0	0
T242	3516	45	0	0
T243	4676	74	0	0
T245	43687	244	0	0
T254	9441	57	0	0
T257	10306	56	0	0
T258	9910	48	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3617	0	0
T190	23292	54	0	0
T192	8884	103	0	0
T231	6337	4	0	0
T232	24033	249	0	0
T242	3516	2	0	0
T243	4676	47	0	0
T245	43687	215	0	0
T254	9441	11	0	0
T257	10306	46	0	0
T258	9910	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	4700	0	0
T190	23292	302	0	0
T192	8884	145	0	0
T199	2703	18	0	0
T231	6337	54	0	0
T243	4676	77	0	0
T254	9441	41	0	0
T257	10306	31	0	0
T258	9910	70	0	0
T263	2358	6	0	0
T264	2192	11	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3651	0	0
T190	23292	258	0	0
T192	8884	14	0	0
T210	15107	9	0	0
T231	6337	27	0	0
T232	24033	225	0	0
T242	3516	3	0	0
T243	4676	49	0	0
T254	9441	37	0	0
T257	10306	20	0	0
T258	9910	82	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	2243	0	0
T190	23292	100	0	0
T192	8884	34	0	0
T210	15107	3	0	0
T231	6337	14	0	0
T232	24033	47	0	0
T242	3516	20	0	0
T243	4676	44	0	0
T254	9441	41	0	0
T257	10306	52	0	0
T258	9910	46	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3161	0	0
T190	23292	172	0	0
T192	8884	55	0	0
T231	6337	7	0	0
T232	24033	262	0	0
T242	3516	28	0	0
T243	4676	42	0	0
T245	43687	228	0	0
T254	9441	62	0	0
T257	10306	36	0	0
T258	9910	37	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	4086	0	0
T190	23292	257	0	0
T192	8884	51	0	0
T231	6337	4	0	0
T232	24033	448	0	0
T242	3516	39	0	0
T243	4676	36	0	0
T245	43687	216	0	0
T254	9441	65	0	0
T257	10306	51	0	0
T258	9910	41	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	523833492	3714	0	0
T190	23292	267	0	0
T192	8884	13	0	0
T231	6337	5	0	0
T232	24033	284	0	0
T242	3516	49	0	0
T243	4676	1	0	0
T245	43687	228	0	0
T254	9441	21	0	0
T257	10306	27	0	0
T258	9910	40	0	0