Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17346152	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18180389	1		T1	4		T2	3746		T3	6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34843515	1		T1	2		T2	2063		T3	3
values[0x0]	340891	1		T1	3		T2	918		T3	5
values[0x1]	342135	1		T1	5		T2	951		T3	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13834550	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21691991	1		T1	6		T2	3775		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	138387	1		T2	18		T29	25		T31	12
valid_sources[0x01]	326320	1		T2	16		T29	32		T33	344
valid_sources[0x02]	135653	1		T2	25		T28	2		T29	35
valid_sources[0x03]	240038	1		T2	11		T29	30		T32	2
valid_sources[0x04]	107260	1		T2	26		T29	27		T33	363
valid_sources[0x05]	106816	1		T2	16		T3	1		T29	45
valid_sources[0x06]	161695	1		T2	14		T28	3		T29	36
valid_sources[0x07]	106602	1		T2	12		T3	1		T34	10
valid_sources[0x08]	110419	1		T2	11		T29	38		T33	325
valid_sources[0x09]	108855	1		T2	22		T28	1		T29	36
valid_sources[0x0a]	107000	1		T2	12		T29	39		T33	338
valid_sources[0x0b]	127502	1		T2	15		T29	44		T33	348
valid_sources[0x0c]	108023	1		T2	13		T28	3		T29	43
valid_sources[0x0d]	106670	1		T2	8		T28	3		T29	34
valid_sources[0x0e]	200424	1		T2	14		T29	41		T33	345
valid_sources[0x0f]	127483	1		T2	21		T28	3		T29	38
valid_sources[0x10]	107248	1		T2	14		T29	32		T33	327
valid_sources[0x11]	108248	1		T2	18		T29	38		T33	390
valid_sources[0x12]	133653	1		T2	11		T28	1		T29	40
valid_sources[0x13]	122140	1		T2	15		T28	1		T29	35
valid_sources[0x14]	109396	1		T2	21		T29	28		T33	392
valid_sources[0x15]	107275	1		T2	9		T29	44		T33	343
valid_sources[0x16]	106537	1		T2	21		T28	2		T29	27
valid_sources[0x17]	124452	1		T2	17		T29	34		T33	379
valid_sources[0x18]	106819	1		T2	17		T29	43		T33	347
valid_sources[0x19]	110374	1		T2	15		T29	34		T33	373
valid_sources[0x1a]	134933	1		T2	14		T29	33		T33	321
valid_sources[0x1b]	226391	1		T2	23		T29	30		T33	309
valid_sources[0x1c]	278731	1		T2	14		T28	2		T29	41
valid_sources[0x1d]	107953	1		T2	15		T3	1		T29	35
valid_sources[0x1e]	108733	1		T2	19		T35	2		T29	41
valid_sources[0x1f]	108631	1		T2	11		T35	2		T29	36
valid_sources[0x20]	125353	1		T2	15		T28	2		T29	37
valid_sources[0x21]	108107	1		T2	18		T29	33		T33	379
valid_sources[0x22]	106657	1		T2	11		T29	33		T33	287
valid_sources[0x23]	107619	1		T2	15		T29	23		T33	311
valid_sources[0x24]	107256	1		T2	15		T28	1		T29	28
valid_sources[0x25]	108623	1		T2	10		T29	40		T33	348
valid_sources[0x26]	107324	1		T2	18		T29	27		T33	353
valid_sources[0x27]	105642	1		T2	23		T29	44		T33	375
valid_sources[0x28]	132859	1		T2	15		T29	36		T33	374
valid_sources[0x29]	108698	1		T2	16		T29	45		T33	290
valid_sources[0x2a]	123387	1		T2	16		T29	30		T33	342
valid_sources[0x2b]	107181	1		T2	19		T28	1		T29	28
valid_sources[0x2c]	107561	1		T2	18		T29	22		T33	337
valid_sources[0x2d]	281771	1		T2	14		T29	45		T33	424
valid_sources[0x2e]	107393	1		T2	14		T29	32		T33	359
valid_sources[0x2f]	105400	1		T2	25		T29	31		T33	405
valid_sources[0x30]	107394	1		T2	17		T29	28		T33	326
valid_sources[0x31]	107284	1		T2	16		T29	40		T33	332
valid_sources[0x32]	107993	1		T2	8		T28	2		T29	29
valid_sources[0x33]	154398	1		T2	14		T29	26		T33	377
valid_sources[0x34]	108700	1		T2	19		T29	34		T33	328
valid_sources[0x35]	300814	1		T2	16		T29	38		T4	150375
valid_sources[0x36]	107581	1		T2	9		T29	25		T33	462
valid_sources[0x37]	107306	1		T2	13		T29	33		T33	344
valid_sources[0x38]	107786	1		T2	9		T29	50		T33	415
valid_sources[0x39]	272846	1		T2	16		T28	2		T29	46
valid_sources[0x3a]	333067	1		T2	12		T29	44		T33	360
valid_sources[0x3b]	105300	1		T2	22		T29	39		T33	364
valid_sources[0x3c]	105815	1		T2	25		T29	28		T33	390
valid_sources[0x3d]	242348	1		T2	12		T29	36		T33	283
valid_sources[0x3e]	125776	1		T2	17		T29	40		T33	368
valid_sources[0x3f]	243486	1		T2	18		T35	1		T29	31
valid_sources[0x40]	105873	1		T2	11		T28	2		T29	39
valid_sources[0x41]	108872	1		T2	16		T29	36		T33	358
valid_sources[0x42]	218085	1		T2	18		T29	41		T33	300
valid_sources[0x43]	226361	1		T2	19		T29	32		T33	396
valid_sources[0x44]	274465	1		T2	10		T29	25		T33	333
valid_sources[0x45]	382625	1		T2	13		T29	31		T33	381
valid_sources[0x46]	106994	1		T2	7		T29	32		T33	312
valid_sources[0x47]	124106	1		T2	13		T29	35		T33	358
valid_sources[0x48]	128030	1		T2	18		T29	42		T33	324
valid_sources[0x49]	107258	1		T2	18		T29	32		T33	398
valid_sources[0x4a]	108611	1		T2	24		T3	2		T29	45
valid_sources[0x4b]	107571	1		T2	16		T29	32		T33	391
valid_sources[0x4c]	107364	1		T2	25		T29	35		T33	356
valid_sources[0x4d]	107403	1		T2	15		T29	35		T33	384
valid_sources[0x4e]	107768	1		T2	13		T28	1		T29	30
valid_sources[0x4f]	108190	1		T1	2		T2	15		T28	1
valid_sources[0x50]	119090	1		T2	11		T28	2		T29	32
valid_sources[0x51]	110854	1		T2	5		T29	29		T33	336
valid_sources[0x52]	108891	1		T2	16		T28	1		T29	41
valid_sources[0x53]	106177	1		T2	8		T29	31		T33	260
valid_sources[0x54]	350166	1		T2	19		T28	1		T29	40
valid_sources[0x55]	107827	1		T2	14		T28	2		T29	33
valid_sources[0x56]	107847	1		T2	14		T29	48		T33	333
valid_sources[0x57]	106603	1		T2	17		T29	49		T33	378
valid_sources[0x58]	109612	1		T2	20		T28	1		T29	35
valid_sources[0x59]	107471	1		T2	11		T29	41		T33	381
valid_sources[0x5a]	108001	1		T1	1		T2	15		T28	1
valid_sources[0x5b]	170801	1		T2	13		T29	33		T33	324
valid_sources[0x5c]	108074	1		T2	16		T28	1		T29	33
valid_sources[0x5d]	106798	1		T2	24		T29	28		T33	385
valid_sources[0x5e]	182497	1		T2	11		T29	34		T33	346
valid_sources[0x5f]	106982	1		T2	21		T29	39		T33	381
valid_sources[0x60]	108841	1		T2	6		T28	2		T29	32
valid_sources[0x61]	107039	1		T2	16		T29	32		T33	404
valid_sources[0x62]	361045	1		T2	24		T29	40		T33	366
valid_sources[0x63]	130153	1		T2	12		T28	1		T29	40
valid_sources[0x64]	131409	1		T2	15		T29	50		T33	314
valid_sources[0x65]	257697	1		T2	16		T28	2		T29	39
valid_sources[0x66]	223741	1		T2	13		T28	1		T29	25
valid_sources[0x67]	141703	1		T2	12		T29	29		T33	393
valid_sources[0x68]	237232	1		T2	7		T29	30		T33	342
valid_sources[0x69]	105744	1		T2	20		T29	41		T33	354
valid_sources[0x6a]	125053	1		T2	17		T29	31		T33	400
valid_sources[0x6b]	108703	1		T2	28		T29	26		T33	360
valid_sources[0x6c]	138792	1		T2	18		T29	44		T33	369
valid_sources[0x6d]	224127	1		T2	11		T29	38		T33	408
valid_sources[0x6e]	107441	1		T2	17		T29	39		T33	355
valid_sources[0x6f]	107740	1		T2	7		T28	1		T29	36
valid_sources[0x70]	106896	1		T2	17		T29	37		T33	321
valid_sources[0x71]	107904	1		T2	6		T29	37		T33	299
valid_sources[0x72]	107526	1		T2	14		T29	38		T33	405
valid_sources[0x73]	109503	1		T2	11		T29	23		T33	348
valid_sources[0x74]	107623	1		T2	18		T29	41		T33	338
valid_sources[0x75]	134825	1		T2	13		T29	42		T33	416
valid_sources[0x76]	107900	1		T2	15		T3	3		T29	38
valid_sources[0x77]	128010	1		T2	18		T29	35		T33	374
valid_sources[0x78]	133952	1		T2	11		T28	2		T29	44
valid_sources[0x79]	108329	1		T2	15		T29	36		T33	336
valid_sources[0x7a]	108651	1		T2	12		T28	3		T29	32
valid_sources[0x7b]	135030	1		T2	17		T29	29		T5	28531
valid_sources[0x7c]	106600	1		T1	2		T2	18		T29	48
valid_sources[0x7d]	109828	1		T2	9		T28	3		T29	33
valid_sources[0x7e]	140733	1		T2	18		T28	2		T29	43
valid_sources[0x7f]	110300	1		T2	16		T29	32		T33	331
valid_sources[0x80]	266881	1		T2	18		T35	3		T29	49

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17627959

1

T1

2

T2

1985

T3

1

values[0x0]

all_enables

biggest_size

283910

1

T1

1

T2

870

T3

3

values[0x1]

all_enables

biggest_size

268520

1

T1

1

T2

891

T3

2