Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17361084	1		T1	6		T2	186		T3	6
full_word	18181358	1		T1	4		T2	3746		T3	6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35542102	1		T1	10		T2	3932		T3	12
auto[TlIntgErrCmd]	110	1		T195	7		T220	8		T222	9
auto[TlIntgErrData]	119	1		T195	4		T220	6		T222	8
auto[TlIntgErrBoth]	111	1		T195	9		T220	6		T222	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34845370	1		T1	2		T2	2063		T3	3
auto[1]	697072	1		T1	8		T2	1869		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17217092	1		T2	78		T3	2		T34	2
auto[TlIntgErrNone]	partial	auto[1]	143689	1		T1	6		T2	108		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	17628133	1		T1	2		T2	1985		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	553188	1		T1	2		T2	1761		T3	5
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T195	2		T220	2		T222	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T195	4		T220	4		T222	5
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T264	1		T287	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T195	1		T220	2		T222	1
auto[TlIntgErrData]	partial	auto[0]	50	1		T195	3		T220	1		T222	4
auto[TlIntgErrData]	partial	auto[1]	54	1		T220	4		T222	3		T264	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T195	1		T288	1		T289	1
auto[TlIntgErrData]	full_word	auto[1]	10	1		T220	1		T222	1		T264	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T195	4		T220	2		T222	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T195	5		T220	3		T222	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T222	1		T264	1		T286	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T220	1		T290	1		T291	1