Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	517817012	11431	0	0
ep_in_enable_rd_A	517817012	4443	0	0
ep_out_enable_rd_A	517817012	4328	0	0
in_iso_rd_A	517817012	4553	0	0
intr_enable_rd_A	517817012	5946	0	0
out_iso_rd_A	517817012	4236	0	0
phy_config_rd_A	517817012	2890	0	0
phy_pins_drive_rd_A	517817012	3464	0	0
rxenable_setup_rd_A	517817012	4312	0	0
set_nak_out_rd_A	517817012	4539	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	11431	0	0
T194	4966	304	0	0
T195	70126	1	0	0
T196	3946	18	0	0
T200	7967	18	0	0
T215	4632	198	0	0
T220	24201	6	0	0
T221	2187	203	0	0
T222	92782	4	0	0
T226	4088	14	0	0
T232	4527	6	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4443	0	0
T200	7967	52	0	0
T231	7822	89	0	0
T243	17018	132	0	0
T245	96091	479	0	0
T247	96062	274	0	0
T257	10204	18	0	0
T259	7101	38	0	0
T260	13419	16	0	0
T264	20227	161	0	0
T265	61909	335	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4328	0	0
T200	7967	83	0	0
T224	13543	3	0	0
T231	7822	104	0	0
T243	17018	115	0	0
T245	96091	435	0	0
T247	96062	237	0	0
T257	10204	27	0	0
T259	7101	27	0	0
T260	13419	55	0	0
T264	20227	126	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4553	0	0
T200	7967	71	0	0
T231	7822	73	0	0
T243	17018	120	0	0
T245	96091	385	0	0
T247	96062	253	0	0
T257	10204	29	0	0
T259	7101	23	0	0
T260	13419	49	0	0
T264	20227	67	0	0
T265	61909	271	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	5946	0	0
T200	7967	98	0	0
T205	2632	30	0	0
T208	4176	20	0	0
T243	17018	101	0	0
T245	96091	480	0	0
T257	10204	34	0	0
T259	7101	31	0	0
T264	20227	134	0	0
T266	2698	7	0	0
T267	1835	10	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4236	0	0
T200	7967	15	0	0
T231	7822	73	0	0
T243	17018	75	0	0
T245	96091	506	0	0
T247	96062	260	0	0
T257	10204	15	0	0
T259	7101	4	0	0
T260	13419	55	0	0
T264	20227	85	0	0
T265	61909	234	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	2890	0	0
T200	7967	51	0	0
T231	7822	21	0	0
T243	17018	84	0	0
T245	96091	402	0	0
T247	96062	249	0	0
T257	10204	2	0	0
T259	7101	4	0	0
T260	13419	33	0	0
T264	20227	47	0	0
T265	61909	112	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	3464	0	0
T200	7967	50	0	0
T231	7822	45	0	0
T243	17018	116	0	0
T245	96091	406	0	0
T247	96062	250	0	0
T257	10204	47	0	0
T259	7101	27	0	0
T260	13419	25	0	0
T264	20227	122	0	0
T265	61909	202	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4312	0	0
T200	7967	89	0	0
T231	7822	39	0	0
T243	17018	119	0	0
T245	96091	423	0	0
T247	96062	259	0	0
T257	10204	27	0	0
T259	7101	48	0	0
T260	13419	28	0	0
T264	20227	114	0	0
T265	61909	259	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	517817012	4539	0	0
T200	7967	99	0	0
T231	7822	105	0	0
T243	17018	160	0	0
T245	96091	479	0	0
T247	96062	254	0	0
T257	10204	24	0	0
T259	7101	22	0	0
T260	13419	33	0	0
T264	20227	114	0	0
T265	61909	266	0	0