Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.63	100.00	88.89				50.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic	68.52	100.00	55.56				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic	72.22	100.00	66.67				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic	75.93	100.00	77.78				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic	75.93	100.00	77.78				50.00
tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic	79.63	100.00	88.89				50.00

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.52	100.00	55.56				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.52	100.00	55.56				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_se0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.22	100.00	66.67				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
72.22	100.00	66.67				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_dn

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.93	100.00	77.78				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_oe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.63	100.00	88.89				50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.63	100.00	88.89				50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							i_mux_tx_dp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T26,T27
1	1	Covered	T22,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T26,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	14391637	14379329	0	0
selKnown1	81	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	14391637	14379329	0	0
T2	15958	15953	0	0
T3	66	61	0	0
T4	17289	17284	0	0
T5	6145	17906	0	0
T6	6858	19783	0	0
T28	426	421	0	0
T29	310	305	0	0
T30	282	277	0	0
T31	22	17	0	0
T32	330	325	0	0
T33	0	298	0	0
T34	2	0	0	0
T35	2	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	81	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T28
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T26,T27
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T28

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	153605	151371	0	0
selKnown1	0	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	153605	151371	0	0
T2	313	312	0	0
T3	2	1	0	0
T4	165	164	0	0
T5	146	145	0	0
T6	219	218	0	0
T28	14	13	0	0
T29	7	6	0	0
T30	8	7	0	0
T31	1	0	0	0
T32	2	1	0	0
T33	0	149	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	6	66.67
Logical	9	6	66.67
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T28
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T22,T26,T27
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T26,T27
1	0	Covered	T2,T3,T28
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	1	50.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	1	50.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4702449	4699647	0	0
selKnown1	0	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4702449	4699647	0	0
T2	5121	5120	0	0
T3	21	20	0	0
T4	5664	5663	0	0
T5	0	5882	0	0
T6	0	6464	0	0
T28	133	132	0	0
T29	99	98	0	0
T30	89	88	0	0
T31	7	6	0	0
T32	109	108	0	0
T34	1	0	0	0
T35	1	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T28
1	0	Covered	T22,T27,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T37,T38
1	1	Covered	T22,T27,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T28

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4679528	4677293	0	0
selKnown1	26	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4679528	4677293	0	0
T2	5090	5089	0	0
T3	20	19	0	0
T4	5631	5630	0	0
T5	5853	5852	0	0
T6	6420	6419	0	0
T28	132	131	0	0
T29	98	97	0	0
T30	88	87	0	0
T31	6	5	0	0
T32	108	107	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	26	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T28
1	0	Covered	T22,T27,T37

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T26,T36,T38
1	1	Covered	T22,T27,T37

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T28

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	153606	151371	0	0
selKnown1	27	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	153606	151371	0	0
T2	313	312	0	0
T3	2	1	0	0
T4	165	164	0	0
T5	146	145	0	0
T6	219	218	0	0
T28	14	13	0	0
T29	7	6	0	0
T30	8	7	0	0
T31	1	0	0	0
T32	2	1	0	0
T33	0	149	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	27	0	0	0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T28
0	1	Covered	T1,T2,T3
1	0	Covered	T22,T26,T36

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T27,T39,T40
1	1	Covered	T22,T26,T36

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T22,T26,T27
1	0	Covered	T2,T3,T28
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	1	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	1	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	4702449	4699647	0	0
selKnown1	28	0	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	4702449	4699647	0	0
T2	5121	5120	0	0
T3	21	20	0	0
T4	5664	5663	0	0
T5	0	5882	0	0
T6	0	6464	0	0
T28	133	132	0	0
T29	99	98	0	0
T30	89	88	0	0
T31	7	6	0	0
T32	109	108	0	0
T34	1	0	0	0
T35	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	28	0	0	0