Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	17181231	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	18055342	1		T1	24		T2	6		T3	14131

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	34553756	1		T1	12		T2	3		T3	27770
values[0x0]	340900	1		T1	11		T2	7		T3	28
values[0x1]	341917	1		T1	13		T2	2		T3	36

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13700274	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21536299	1		T1	28		T2	7		T3	16913

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	99640	1		T3	134		T4	337		T30	72
valid_sources[0x01]	121932	1		T3	80		T4	328		T30	78
valid_sources[0x02]	134436	1		T3	79		T4	354		T30	85
valid_sources[0x03]	98982	1		T3	117		T4	368		T30	54
valid_sources[0x04]	100197	1		T3	115		T4	296		T30	91
valid_sources[0x05]	99571	1		T3	151		T4	331		T30	81
valid_sources[0x06]	99861	1		T3	88		T4	336		T30	79
valid_sources[0x07]	308857	1		T3	108		T4	328		T30	57
valid_sources[0x08]	164398	1		T3	101		T4	340		T30	94
valid_sources[0x09]	104950	1		T3	115		T4	330		T30	95
valid_sources[0x0a]	117060	1		T3	122		T4	315		T30	85
valid_sources[0x0b]	99891	1		T3	152		T4	334		T30	88
valid_sources[0x0c]	99552	1		T3	92		T4	315		T30	85
valid_sources[0x0d]	119926	1		T3	100		T4	321		T30	94
valid_sources[0x0e]	100149	1		T3	117		T29	1		T4	332
valid_sources[0x0f]	98077	1		T3	97		T4	347		T30	70
valid_sources[0x10]	103733	1		T3	74		T4	331		T30	84
valid_sources[0x11]	98448	1		T3	83		T4	330		T30	85
valid_sources[0x12]	126801	1		T3	96		T4	370		T30	104
valid_sources[0x13]	120081	1		T3	96		T4	336		T30	76
valid_sources[0x14]	140062	1		T3	115		T4	341		T30	93
valid_sources[0x15]	141535	1		T3	133		T4	354		T30	62
valid_sources[0x16]	123909	1		T3	143		T4	343		T30	79
valid_sources[0x17]	99354	1		T3	95		T4	343		T30	134
valid_sources[0x18]	99165	1		T3	57		T4	347		T30	69
valid_sources[0x19]	99652	1		T3	99		T4	339		T30	77
valid_sources[0x1a]	100692	1		T3	127		T4	356		T30	83
valid_sources[0x1b]	100179	1		T3	130		T4	353		T30	51
valid_sources[0x1c]	99789	1		T3	104		T4	283		T30	59
valid_sources[0x1d]	119294	1		T3	91		T4	351		T30	70
valid_sources[0x1e]	98164	1		T3	116		T29	1		T4	317
valid_sources[0x1f]	99791	1		T3	124		T4	360		T30	63
valid_sources[0x20]	98467	1		T3	103		T4	341		T30	92
valid_sources[0x21]	98662	1		T3	119		T4	317		T30	71
valid_sources[0x22]	102475	1		T3	133		T4	339		T30	59
valid_sources[0x23]	99089	1		T3	120		T4	318		T30	76
valid_sources[0x24]	99115	1		T3	129		T4	315		T30	80
valid_sources[0x25]	195198	1		T3	86		T4	348		T30	73
valid_sources[0x26]	99364	1		T3	139		T4	349		T30	74
valid_sources[0x27]	317389	1		T3	60		T4	332		T30	78
valid_sources[0x28]	101137	1		T3	102		T4	362		T30	72
valid_sources[0x29]	281330	1		T3	122		T4	326		T30	81
valid_sources[0x2a]	99295	1		T3	109		T4	333		T30	71
valid_sources[0x2b]	98998	1		T3	112		T4	375		T30	85
valid_sources[0x2c]	98641	1		T3	117		T4	313		T30	67
valid_sources[0x2d]	99515	1		T3	104		T4	353		T30	88
valid_sources[0x2e]	100235	1		T3	130		T4	325		T30	67
valid_sources[0x2f]	191788	1		T3	108		T4	330		T30	60
valid_sources[0x30]	260672	1		T3	96		T4	311		T30	88
valid_sources[0x31]	99754	1		T3	93		T4	310		T30	101
valid_sources[0x32]	100442	1		T3	120		T4	373		T30	77
valid_sources[0x33]	100671	1		T3	117		T4	314		T30	95
valid_sources[0x34]	296538	1		T3	126		T4	350		T30	94
valid_sources[0x35]	217704	1		T3	117		T4	287		T30	93
valid_sources[0x36]	291425	1		T3	107		T4	333		T30	59
valid_sources[0x37]	99086	1		T3	103		T4	311		T30	95
valid_sources[0x38]	100183	1		T3	82		T4	319		T30	94
valid_sources[0x39]	101147	1		T3	130		T4	338		T30	65
valid_sources[0x3a]	150051	1		T3	106		T4	325		T30	88
valid_sources[0x3b]	99266	1		T3	94		T4	302		T30	64
valid_sources[0x3c]	117648	1		T3	112		T4	350		T30	83
valid_sources[0x3d]	257785	1		T3	129		T4	341		T30	74
valid_sources[0x3e]	281042	1		T3	120		T4	326		T30	67
valid_sources[0x3f]	242276	1		T3	117		T4	334		T30	104
valid_sources[0x40]	101112	1		T3	90		T4	334		T30	98
valid_sources[0x41]	258239	1		T3	157		T4	342		T30	64
valid_sources[0x42]	219976	1		T3	139		T4	333		T30	86
valid_sources[0x43]	100958	1		T3	99		T4	326		T30	85
valid_sources[0x44]	101105	1		T3	95		T4	317		T30	94
valid_sources[0x45]	309552	1		T3	114		T4	311		T30	87
valid_sources[0x46]	122547	1		T3	134		T4	304		T30	66
valid_sources[0x47]	108492	1		T3	124		T4	303		T30	60
valid_sources[0x48]	204838	1		T3	123		T4	329		T30	96
valid_sources[0x49]	100036	1		T3	88		T4	305		T30	77
valid_sources[0x4a]	159036	1		T3	144		T4	383		T30	90
valid_sources[0x4b]	99899	1		T3	118		T4	331		T30	66
valid_sources[0x4c]	234216	1		T3	80		T4	351		T30	81
valid_sources[0x4d]	491558	1		T3	106		T4	323		T30	69
valid_sources[0x4e]	101278	1		T3	110		T4	315		T30	99
valid_sources[0x4f]	99347	1		T3	89		T4	295		T30	59
valid_sources[0x50]	97528	1		T3	130		T4	321		T30	79
valid_sources[0x51]	267075	1		T3	117		T4	368		T30	50
valid_sources[0x52]	98168	1		T3	130		T4	295		T30	103
valid_sources[0x53]	99982	1		T3	121		T4	306		T30	86
valid_sources[0x54]	99643	1		T3	71		T4	340		T30	90
valid_sources[0x55]	100523	1		T3	74		T4	347		T30	105
valid_sources[0x56]	99888	1		T3	102		T4	312		T30	68
valid_sources[0x57]	122668	1		T3	110		T4	303		T30	68
valid_sources[0x58]	99129	1		T3	81		T29	2		T4	354
valid_sources[0x59]	99577	1		T3	113		T4	342		T30	74
valid_sources[0x5a]	100228	1		T3	138		T4	309		T30	80
valid_sources[0x5b]	99945	1		T3	106		T4	342		T30	51
valid_sources[0x5c]	292314	1		T3	80		T4	327		T30	65
valid_sources[0x5d]	98729	1		T3	120		T4	315		T30	69
valid_sources[0x5e]	99301	1		T3	115		T4	300		T30	88
valid_sources[0x5f]	128223	1		T3	99		T4	334		T30	76
valid_sources[0x60]	98522	1		T3	142		T4	356		T30	95
valid_sources[0x61]	99389	1		T2	1		T3	123		T4	326
valid_sources[0x62]	106072	1		T3	118		T4	306		T30	95
valid_sources[0x63]	250453	1		T3	116		T4	313		T30	85
valid_sources[0x64]	154446	1		T3	93		T4	298		T30	86
valid_sources[0x65]	259886	1		T3	92		T4	315		T30	68
valid_sources[0x66]	98958	1		T3	101		T4	318		T30	89
valid_sources[0x67]	98409	1		T3	100		T4	340		T30	75
valid_sources[0x68]	333812	1		T3	120		T4	347		T30	70
valid_sources[0x69]	98319	1		T3	133		T4	342		T30	69
valid_sources[0x6a]	186724	1		T3	98		T4	341		T30	72
valid_sources[0x6b]	145727	1		T3	118		T4	316		T30	91
valid_sources[0x6c]	125307	1		T3	109		T4	368		T30	83
valid_sources[0x6d]	219327	1		T3	103		T4	340		T30	75
valid_sources[0x6e]	123807	1		T3	97		T4	317		T30	82
valid_sources[0x6f]	99157	1		T3	71		T4	322		T30	72
valid_sources[0x70]	99608	1		T3	91		T4	340		T30	61
valid_sources[0x71]	99516	1		T2	3		T3	152		T4	336
valid_sources[0x72]	191541	1		T3	86		T4	327		T30	64
valid_sources[0x73]	132481	1		T3	117		T4	316		T30	81
valid_sources[0x74]	99794	1		T3	95		T4	312		T30	66
valid_sources[0x75]	103896	1		T3	112		T4	313		T30	61
valid_sources[0x76]	99253	1		T3	124		T4	344		T30	87
valid_sources[0x77]	127656	1		T3	100		T4	319		T30	68
valid_sources[0x78]	97164	1		T3	134		T4	322		T30	87
valid_sources[0x79]	98631	1		T3	71		T4	315		T30	85
valid_sources[0x7a]	100021	1		T3	81		T4	341		T30	90
valid_sources[0x7b]	98838	1		T3	98		T4	371		T30	47
valid_sources[0x7c]	99803	1		T3	83		T29	1		T4	309
valid_sources[0x7d]	98698	1		T3	94		T4	342		T30	98
valid_sources[0x7e]	203499	1		T3	108		T4	315		T30	74
valid_sources[0x7f]	143365	1		T3	90		T4	335		T30	81
valid_sources[0x80]	99129	1		T3	119		T4	324		T30	53

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

17503929

1

T1

7

T2

1

T3

14085

values[0x0]

all_enables

biggest_size

283776

1

T1

9

T2

4

T3

19

values[0x1]

all_enables

biggest_size

267637

1

T1

8

T2

1

T3

27