Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	17199525	1		T1	12		T2	6		T3	13703
full_word	18056630	1		T1	24		T2	6		T3	14131

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35255865	1		T1	36		T2	12		T3	27834
auto[TlIntgErrCmd]	98	1		T188	3		T215	4		T222	7
auto[TlIntgErrData]	100	1		T188	5		T215	3		T222	4
auto[TlIntgErrBoth]	92	1		T188	2		T215	3		T222	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	34556205	1		T1	12		T2	3		T3	27770
auto[1]	699950	1		T1	24		T2	9		T3	64

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17051925	1		T1	5		T2	2		T3	13685
auto[TlIntgErrNone]	partial	auto[1]	147337	1		T1	7		T2	4		T3	18
auto[TlIntgErrNone]	full_word	auto[0]	17504157	1		T1	7		T2	1		T3	14085
auto[TlIntgErrNone]	full_word	auto[1]	552446	1		T1	17		T2	5		T3	46
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T188	1		T215	1		T222	4
auto[TlIntgErrCmd]	partial	auto[1]	59	1		T188	1		T215	3		T222	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T188	1		T222	1		T292	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T240	1		T288	1		T289	1
auto[TlIntgErrData]	partial	auto[0]	44	1		T188	2		T215	1		T222	1
auto[TlIntgErrData]	partial	auto[1]	47	1		T188	3		T215	1		T222	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T240	1		T293	1		T294	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T215	1		T290	1		T295	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T215	1		T222	4		T240	4
auto[TlIntgErrBoth]	partial	auto[1]	45	1		T188	2		T215	1		T222	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T215	1		T222	1		T296	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T222	1		T290	1		T297	1