Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	531135783	13902	0	0
ep_in_enable_rd_A	531135783	3645	0	0
ep_out_enable_rd_A	531135783	3823	0	0
in_iso_rd_A	531135783	4018	0	0
intr_enable_rd_A	531135783	5422	0	0
out_iso_rd_A	531135783	4063	0	0
phy_config_rd_A	531135783	2291	0	0
phy_pins_drive_rd_A	531135783	2903	0	0
rxenable_setup_rd_A	531135783	3642	0	0
set_nak_out_rd_A	531135783	3727	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	13902	0	0
T187	14247	639	0	0
T188	26195	1	0	0
T189	5204	30	0	0
T214	8912	9	0	0
T215	18070	3	0	0
T222	43748	9	0	0
T223	10044	585	0	0
T237	8260	13	0	0
T238	4111	15	0	0
T239	7980	11	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	3645	0	0
T214	8912	117	0	0
T222	43748	494	0	0
T233	2706	30	0	0
T237	8260	110	0	0
T239	7980	65	0	0
T240	103396	365	0	0
T258	2617	41	0	0
T261	7659	3	0	0
T270	10939	22	0	0
T276	9160	6	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	3823	0	0
T214	8912	21	0	0
T222	43748	314	0	0
T233	2706	57	0	0
T237	8260	63	0	0
T258	2617	54	0	0
T261	7659	5	0	0
T270	10939	15	0	0
T271	6418	23	0	0
T272	5281	4	0	0
T276	9160	22	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	4018	0	0
T214	8912	27	0	0
T222	43748	635	0	0
T233	2706	46	0	0
T237	8260	45	0	0
T258	2617	52	0	0
T261	7659	9	0	0
T270	10939	47	0	0
T271	6418	14	0	0
T272	5281	23	0	0
T276	9160	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	5422	0	0
T200	1900	14	0	0
T201	1936	7	0	0
T214	8912	80	0	0
T233	2706	7	0	0
T237	8260	156	0	0
T258	2617	5	0	0
T270	10939	36	0	0
T271	6418	6	0	0
T272	5281	10	0	0
T277	1926	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	4063	0	0
T214	8912	13	0	0
T222	43748	567	0	0
T233	2706	5	0	0
T237	8260	61	0	0
T258	2617	47	0	0
T261	7659	6	0	0
T270	10939	68	0	0
T271	6418	5	0	0
T272	5281	5	0	0
T276	9160	23	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	2291	0	0
T187	14247	1	0	0
T214	8912	44	0	0
T222	43748	201	0	0
T233	2706	18	0	0
T237	8260	39	0	0
T258	2617	39	0	0
T270	10939	32	0	0
T271	6418	21	0	0
T272	5281	14	0	0
T276	9160	18	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	2903	0	0
T214	8912	77	0	0
T222	43748	348	0	0
T233	2706	36	0	0
T237	8260	56	0	0
T239	7980	17	0	0
T258	2617	5	0	0
T261	7659	3	0	0
T270	10939	31	0	0
T271	6418	28	0	0
T276	9160	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	3642	0	0
T214	8912	46	0	0
T222	43748	321	0	0
T233	2706	39	0	0
T237	8260	59	0	0
T258	2617	6	0	0
T261	7659	1	0	0
T270	10939	26	0	0
T271	6418	32	0	0
T272	5281	11	0	0
T276	9160	41	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531135783	3727	0	0
T214	8912	85	0	0
T222	43748	458	0	0
T223	10044	1	0	0
T233	2706	5	0	0
T237	8260	60	0	0
T258	2617	7	0	0
T270	10939	46	0	0
T271	6418	20	0	0
T272	5281	23	0	0
T276	9160	18	0	0