Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16398652	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17234296	1		T1	4		T2	15		T3	9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32959142	1		T1	3		T2	10		T3	7
values[0x0]	337166	1		T1	5		T2	7		T3	2
values[0x1]	336640	1		T1	4		T2	9		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13076073	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20556875	1		T1	7		T2	19		T3	13

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	280681	1		T7	1		T4	102		T5	529
valid_sources[0x01]	91878	1		T7	3		T4	114		T5	616
valid_sources[0x02]	93164	1		T4	120		T5	504		T6	274
valid_sources[0x03]	91224	1		T4	120		T5	610		T6	161
valid_sources[0x04]	125030	1		T4	116		T5	499		T6	129
valid_sources[0x05]	91253	1		T4	121		T5	539		T6	79
valid_sources[0x06]	92695	1		T30	1		T4	100		T5	607
valid_sources[0x07]	92956	1		T4	108		T17	3		T5	571
valid_sources[0x08]	125717	1		T4	106		T5	551		T6	178
valid_sources[0x09]	158919	1		T4	102		T5	596		T6	193
valid_sources[0x0a]	260118	1		T1	2		T7	1		T4	111
valid_sources[0x0b]	92077	1		T4	105		T5	602		T6	201
valid_sources[0x0c]	92609	1		T4	95		T5	535		T6	137
valid_sources[0x0d]	91937	1		T4	118		T5	617		T6	254
valid_sources[0x0e]	120927	1		T30	2		T4	112		T5	522
valid_sources[0x0f]	91496	1		T4	127		T5	545		T6	141
valid_sources[0x10]	106272	1		T23	1		T7	1		T4	130
valid_sources[0x11]	108001	1		T30	1		T4	101		T5	530
valid_sources[0x12]	109593	1		T4	136		T5	561		T6	103
valid_sources[0x13]	92525	1		T30	1		T7	3		T4	138
valid_sources[0x14]	94100	1		T4	110		T5	576		T6	89
valid_sources[0x15]	93897	1		T4	102		T5	629		T6	84
valid_sources[0x16]	145822	1		T4	119		T5	551		T6	132
valid_sources[0x17]	92888	1		T4	92		T5	598		T6	179
valid_sources[0x18]	92092	1		T7	1		T4	107		T5	493
valid_sources[0x19]	93886	1		T4	108		T5	591		T6	88
valid_sources[0x1a]	238457	1		T4	114		T5	514		T6	148
valid_sources[0x1b]	227999	1		T4	106		T5	548		T6	149
valid_sources[0x1c]	121065	1		T1	2		T3	1		T4	108
valid_sources[0x1d]	96911	1		T4	106		T5	562		T6	180
valid_sources[0x1e]	119800	1		T4	101		T5	557		T6	232
valid_sources[0x1f]	264078	1		T4	114		T5	624		T6	168
valid_sources[0x20]	94784	1		T4	104		T5	595		T6	173
valid_sources[0x21]	103432	1		T4	103		T5	589		T6	107
valid_sources[0x22]	136864	1		T4	112		T5	543		T6	82
valid_sources[0x23]	142880	1		T4	112		T17	1		T5	508
valid_sources[0x24]	91751	1		T7	5		T4	99		T5	541
valid_sources[0x25]	91468	1		T30	1		T4	126		T5	602
valid_sources[0x26]	92574	1		T7	1		T4	111		T5	547
valid_sources[0x27]	91139	1		T4	127		T5	623		T6	185
valid_sources[0x28]	122458	1		T4	101		T5	536		T6	171
valid_sources[0x29]	118956	1		T4	121		T5	541		T6	191
valid_sources[0x2a]	94141	1		T4	105		T5	586		T6	85
valid_sources[0x2b]	111551	1		T4	116		T5	583		T6	123
valid_sources[0x2c]	127917	1		T4	94		T5	631		T6	189
valid_sources[0x2d]	93493	1		T7	3		T4	131		T5	573
valid_sources[0x2e]	93330	1		T4	109		T5	603		T6	95
valid_sources[0x2f]	284441	1		T4	85		T5	564		T6	177
valid_sources[0x30]	97372	1		T4	99		T5	552		T6	125
valid_sources[0x31]	246424	1		T4	85		T5	572		T6	311
valid_sources[0x32]	318945	1		T4	113		T5	653		T6	91
valid_sources[0x33]	91842	1		T4	121		T5	711		T6	34
valid_sources[0x34]	93065	1		T7	1		T4	140		T5	547
valid_sources[0x35]	94275	1		T4	100		T5	528		T6	265
valid_sources[0x36]	156542	1		T4	98		T5	518		T6	299
valid_sources[0x37]	123860	1		T4	103		T5	575		T6	146
valid_sources[0x38]	93340	1		T7	1		T4	123		T5	487
valid_sources[0x39]	93248	1		T4	100		T5	566		T6	89
valid_sources[0x3a]	94370	1		T4	126		T5	550		T6	179
valid_sources[0x3b]	116282	1		T4	105		T5	571		T6	79
valid_sources[0x3c]	196181	1		T4	117		T5	570		T6	312
valid_sources[0x3d]	92958	1		T4	97		T5	516		T6	105
valid_sources[0x3e]	91596	1		T7	1		T4	123		T5	661
valid_sources[0x3f]	93427	1		T7	1		T4	104		T5	640
valid_sources[0x40]	91070	1		T4	95		T5	524		T6	113
valid_sources[0x41]	230421	1		T4	140		T5	525		T6	108
valid_sources[0x42]	126515	1		T4	117		T18	1		T5	639
valid_sources[0x43]	92527	1		T7	1		T4	77		T18	1
valid_sources[0x44]	108060	1		T4	117		T5	599		T6	114
valid_sources[0x45]	92086	1		T7	5		T4	100		T5	618
valid_sources[0x46]	137202	1		T3	1		T4	106		T5	530
valid_sources[0x47]	190457	1		T4	125		T5	610		T6	109
valid_sources[0x48]	248135	1		T4	116		T5	514		T6	201
valid_sources[0x49]	93900	1		T30	1		T7	2		T4	98
valid_sources[0x4a]	94686	1		T4	113		T5	513		T6	95
valid_sources[0x4b]	302714	1		T4	113		T5	570		T6	145
valid_sources[0x4c]	92417	1		T4	105		T5	571		T6	131
valid_sources[0x4d]	91683	1		T4	97		T5	598		T6	55
valid_sources[0x4e]	115353	1		T4	109		T5	511		T6	177
valid_sources[0x4f]	93960	1		T4	119		T5	622		T6	93
valid_sources[0x50]	92666	1		T3	2		T4	121		T5	512
valid_sources[0x51]	121744	1		T4	104		T5	601		T6	133
valid_sources[0x52]	95483	1		T4	125		T5	601		T6	210
valid_sources[0x53]	122073	1		T7	1		T4	106		T5	554
valid_sources[0x54]	93853	1		T4	100		T5	590		T6	135
valid_sources[0x55]	92419	1		T4	132		T5	613		T6	194
valid_sources[0x56]	166209	1		T4	110		T5	632		T6	210
valid_sources[0x57]	94904	1		T4	133		T5	559		T6	171
valid_sources[0x58]	131096	1		T7	3		T4	105		T5	611
valid_sources[0x59]	280258	1		T4	106		T17	2		T5	555
valid_sources[0x5a]	397749	1		T4	113		T5	590		T6	233
valid_sources[0x5b]	93357	1		T4	112		T5	549		T6	121
valid_sources[0x5c]	92786	1		T4	117		T5	560		T6	168
valid_sources[0x5d]	94286	1		T4	110		T5	614		T6	176
valid_sources[0x5e]	224546	1		T4	114		T5	480		T6	243
valid_sources[0x5f]	110625	1		T26	28		T4	106		T18	3
valid_sources[0x60]	95362	1		T7	1		T4	111		T5	498
valid_sources[0x61]	102102	1		T7	1		T4	91		T5	657
valid_sources[0x62]	295383	1		T4	89		T5	578		T6	220
valid_sources[0x63]	92150	1		T4	112		T5	597		T6	99
valid_sources[0x64]	313719	1		T4	112		T5	494		T6	146
valid_sources[0x65]	93949	1		T4	115		T5	542		T6	260
valid_sources[0x66]	93001	1		T4	112		T5	573		T6	148
valid_sources[0x67]	189767	1		T7	1		T4	122		T5	619
valid_sources[0x68]	96919	1		T30	1		T4	99		T5	547
valid_sources[0x69]	117688	1		T4	127		T5	576		T6	237
valid_sources[0x6a]	93975	1		T7	2		T4	97		T5	638
valid_sources[0x6b]	92318	1		T3	1		T30	1		T4	118
valid_sources[0x6c]	94140	1		T4	87		T5	595		T6	242
valid_sources[0x6d]	133407	1		T7	1		T4	103		T5	565
valid_sources[0x6e]	93989	1		T4	113		T5	558		T6	219
valid_sources[0x6f]	93006	1		T4	112		T5	560		T6	128
valid_sources[0x70]	94774	1		T7	3		T4	114		T5	594
valid_sources[0x71]	104526	1		T4	108		T5	532		T6	224
valid_sources[0x72]	92754	1		T7	1		T4	107		T5	554
valid_sources[0x73]	372158	1		T7	1		T4	139		T5	548
valid_sources[0x74]	96367	1		T4	107		T5	586		T6	139
valid_sources[0x75]	122398	1		T4	117		T5	572		T6	170
valid_sources[0x76]	115291	1		T7	1		T4	119		T5	572
valid_sources[0x77]	93453	1		T7	1		T4	104		T5	533
valid_sources[0x78]	93906	1		T4	135		T5	424		T6	65
valid_sources[0x79]	113815	1		T7	1		T4	126		T5	543
valid_sources[0x7a]	91988	1		T4	127		T5	567		T6	102
valid_sources[0x7b]	92599	1		T7	1		T4	126		T5	545
valid_sources[0x7c]	145626	1		T23	1		T4	120		T5	577
valid_sources[0x7d]	104210	1		T7	1		T4	108		T5	571
valid_sources[0x7e]	116266	1		T29	14		T7	2		T4	99
valid_sources[0x7f]	91597	1		T4	115		T5	592		T6	81
valid_sources[0x80]	93883	1		T7	2		T4	100		T5	510

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16688681

1

T2

2

T3

5

T29

2

values[0x0]

all_enables

biggest_size

281150

1

T1

3

T2

7

T3

2

values[0x1]

all_enables

biggest_size

264465

1

T1

1

T2

6

T3

2