Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	16413455	1		T1	8		T2	11		T3	7
full_word	17235408	1		T1	4		T2	15		T3	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	33648523	1		T1	12		T2	26		T3	16
auto[TlIntgErrCmd]	112	1		T186	5		T189	8		T212	3
auto[TlIntgErrData]	102	1		T186	4		T189	6		T212	3
auto[TlIntgErrBoth]	126	1		T186	11		T189	6		T212	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	32960996	1		T1	3		T2	10		T3	7
auto[1]	687867	1		T1	9		T2	16		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16271994	1		T1	3		T2	8		T3	2
auto[TlIntgErrNone]	partial	auto[1]	141155	1		T1	5		T2	3		T3	5
auto[TlIntgErrNone]	full_word	auto[0]	16688853	1		T2	2		T3	5		T29	2
auto[TlIntgErrNone]	full_word	auto[1]	546521	1		T1	4		T2	13		T3	4
auto[TlIntgErrCmd]	partial	auto[0]	50	1		T186	3		T189	3		T212	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T186	2		T189	5		T212	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T235	1		T277	1		T304	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T308	1		T276	1		T309	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T186	2		T189	3		T212	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T186	1		T189	2		T212	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T186	1		T277	1		T310	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T189	1		T212	1		T309	2
auto[TlIntgErrBoth]	partial	auto[0]	45	1		T186	6		T212	2		T235	1
auto[TlIntgErrBoth]	partial	auto[1]	72	1		T186	5		T189	6		T212	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T224	1		T308	1		T230	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T212	1		T224	1		T277	1