Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	522259127	11230	0	0
ep_in_enable_rd_A	522259127	3394	0	0
ep_out_enable_rd_A	522259127	3047	0	0
in_iso_rd_A	522259127	3552	0	0
intr_enable_rd_A	522259127	4182	0	0
out_iso_rd_A	522259127	2880	0	0
phy_config_rd_A	522259127	2258	0	0
phy_pins_drive_rd_A	522259127	2724	0	0
rxenable_setup_rd_A	522259127	3531	0	0
set_nak_out_rd_A	522259127	3831	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	11230	0	0
T186	25293	4	0	0
T187	4932	8	0	0
T188	5171	7	0	0
T189	37881	3	0	0
T207	4236	287	0	0
T212	22682	1	0	0
T215	3360	256	0	0
T216	4442	555	0	0
T231	5662	10	0	0
T232	4227	19	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	3394	0	0
T188	5171	50	0	0
T209	6556	6	0	0
T212	22682	239	0	0
T227	5605	69	0	0
T254	73090	512	0	0
T257	3044	18	0	0
T265	15797	50	0	0
T275	8491	9	0	0
T276	26154	227	0	0
T277	81880	470	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	3047	0	0
T188	5171	10	0	0
T209	6556	62	0	0
T212	22682	183	0	0
T227	5605	6	0	0
T254	73090	527	0	0
T257	3044	1	0	0
T265	15797	31	0	0
T275	8491	7	0	0
T276	26154	206	0	0
T277	81880	323	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	3552	0	0
T188	5171	10	0	0
T209	6556	3	0	0
T212	22682	272	0	0
T227	5605	51	0	0
T254	73090	500	0	0
T257	3044	54	0	0
T265	15797	32	0	0
T275	8491	1	0	0
T276	26154	324	0	0
T277	81880	429	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	4182	0	0
T188	5171	8	0	0
T209	6556	116	0	0
T212	22682	175	0	0
T254	73090	417	0	0
T257	3044	43	0	0
T265	15797	54	0	0
T275	8491	20	0	0
T276	26154	288	0	0
T278	3541	29	0	0
T279	2450	26	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	2880	0	0
T188	5171	14	0	0
T209	6556	55	0	0
T212	22682	159	0	0
T227	5605	16	0	0
T254	73090	432	0	0
T257	3044	2	0	0
T265	15797	47	0	0
T275	8491	10	0	0
T276	26154	145	0	0
T277	81880	560	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	2258	0	0
T188	5171	17	0	0
T209	6556	31	0	0
T212	22682	123	0	0
T227	5605	34	0	0
T254	73090	368	0	0
T257	3044	22	0	0
T265	15797	39	0	0
T275	8491	12	0	0
T276	26154	109	0	0
T277	81880	307	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	2724	0	0
T188	5171	6	0	0
T209	6556	50	0	0
T212	22682	224	0	0
T227	5605	35	0	0
T254	73090	420	0	0
T257	3044	4	0	0
T265	15797	33	0	0
T275	8491	1	0	0
T276	26154	127	0	0
T277	81880	404	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	3531	0	0
T188	5171	11	0	0
T209	6556	86	0	0
T212	22682	280	0	0
T227	5605	45	0	0
T254	73090	445	0	0
T257	3044	2	0	0
T265	15797	44	0	0
T275	8491	8	0	0
T276	26154	84	0	0
T277	81880	633	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522259127	3831	0	0
T188	5171	60	0	0
T212	22682	369	0	0
T227	5605	17	0	0
T254	73090	446	0	0
T257	3044	24	0	0
T259	15835	111	0	0
T265	15797	55	0	0
T275	8491	11	0	0
T276	26154	194	0	0
T277	81880	658	0	0