Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8922259	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	9674981	1		T1	21		T2	5		T3	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	18037109	1		T1	35		T2	3		T3	2
values[0x0]	279298	1		T1	18		T3	1		T10	5
values[0x1]	280833	1		T1	7		T2	9		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7106940	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	11490300	1		T1	33		T2	9		T3	6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	59936	1		T4	694		T5	250		T16	16
valid_sources[0x01]	72428	1		T4	701		T5	237		T16	14
valid_sources[0x02]	59445	1		T4	845		T5	272		T16	29
valid_sources[0x03]	69291	1		T1	1		T4	763		T5	243
valid_sources[0x04]	60306	1		T4	731		T5	229		T16	20
valid_sources[0x05]	59808	1		T4	634		T5	273		T16	12
valid_sources[0x06]	59162	1		T10	1		T4	617		T5	209
valid_sources[0x07]	58554	1		T4	778		T5	265		T16	17
valid_sources[0x08]	60451	1		T4	585		T5	257		T16	19
valid_sources[0x09]	60746	1		T4	582		T5	257		T16	7
valid_sources[0x0a]	60342	1		T1	1		T10	2		T4	699
valid_sources[0x0b]	76969	1		T4	673		T5	261		T16	10
valid_sources[0x0c]	59215	1		T1	3		T10	3		T4	658
valid_sources[0x0d]	58369	1		T4	772		T5	247		T16	21
valid_sources[0x0e]	59281	1		T4	681		T5	242		T16	5
valid_sources[0x0f]	97931	1		T4	890		T5	240		T16	21
valid_sources[0x10]	64695	1		T1	3		T4	398		T5	267
valid_sources[0x11]	115491	1		T4	731		T5	243		T16	4
valid_sources[0x12]	90127	1		T4	719		T5	259		T16	13
valid_sources[0x13]	60029	1		T4	599		T5	232		T16	6
valid_sources[0x14]	58311	1		T2	3		T4	792		T5	309
valid_sources[0x15]	60842	1		T4	777		T5	261		T16	20
valid_sources[0x16]	105534	1		T4	621		T5	260		T16	24
valid_sources[0x17]	121396	1		T4	634		T5	267		T16	23
valid_sources[0x18]	186325	1		T4	475		T5	215		T16	20
valid_sources[0x19]	59709	1		T4	594		T5	291		T16	19
valid_sources[0x1a]	83665	1		T1	2		T4	810		T5	252
valid_sources[0x1b]	59758	1		T4	420		T5	241		T16	6
valid_sources[0x1c]	60285	1		T4	739		T5	260		T16	19
valid_sources[0x1d]	59721	1		T4	782		T5	239		T16	26
valid_sources[0x1e]	87173	1		T4	683		T5	276		T16	14
valid_sources[0x1f]	58953	1		T4	581		T5	258		T16	35
valid_sources[0x20]	60325	1		T4	641		T5	296		T16	13
valid_sources[0x21]	62360	1		T4	705		T5	261		T16	1
valid_sources[0x22]	59614	1		T4	676		T5	263		T15	2
valid_sources[0x23]	58844	1		T4	558		T5	256		T16	13
valid_sources[0x24]	70320	1		T4	645		T5	261		T16	21
valid_sources[0x25]	76973	1		T4	475		T5	230		T16	8
valid_sources[0x26]	59991	1		T4	553		T5	272		T16	7
valid_sources[0x27]	59341	1		T4	547		T12	1		T5	253
valid_sources[0x28]	71390	1		T4	599		T5	259		T16	21
valid_sources[0x29]	58090	1		T4	570		T5	264		T16	23
valid_sources[0x2a]	60473	1		T4	619		T5	272		T16	25
valid_sources[0x2b]	108511	1		T4	678		T5	260		T16	25
valid_sources[0x2c]	59382	1		T4	846		T5	293		T16	45
valid_sources[0x2d]	68009	1		T4	596		T5	257		T16	8
valid_sources[0x2e]	72089	1		T4	515		T5	259		T16	17
valid_sources[0x2f]	66826	1		T4	614		T5	243		T16	8
valid_sources[0x30]	90575	1		T4	521		T5	256		T16	23
valid_sources[0x31]	74935	1		T4	639		T5	226		T16	14
valid_sources[0x32]	85624	1		T4	539		T5	259		T15	2
valid_sources[0x33]	59033	1		T1	3		T10	1		T4	752
valid_sources[0x34]	68636	1		T1	1		T4	528		T5	277
valid_sources[0x35]	59421	1		T1	1		T4	769		T5	279
valid_sources[0x36]	75531	1		T4	628		T5	268		T16	13
valid_sources[0x37]	59293	1		T4	672		T5	303		T16	25
valid_sources[0x38]	59759	1		T4	777		T5	265		T16	14
valid_sources[0x39]	62925	1		T10	1		T4	767		T5	228
valid_sources[0x3a]	60086	1		T4	765		T5	262		T16	5
valid_sources[0x3b]	78933	1		T4	709		T5	259		T16	28
valid_sources[0x3c]	57770	1		T4	721		T5	233		T16	10
valid_sources[0x3d]	128658	1		T4	626		T12	1		T5	258
valid_sources[0x3e]	59854	1		T1	2		T4	509		T5	277
valid_sources[0x3f]	58961	1		T4	684		T5	256		T16	30
valid_sources[0x40]	70519	1		T4	639		T5	255		T16	11
valid_sources[0x41]	60582	1		T4	633		T5	224		T16	15
valid_sources[0x42]	61900	1		T4	436		T5	282		T16	15
valid_sources[0x43]	59388	1		T4	583		T5	250		T16	22
valid_sources[0x44]	166077	1		T4	768		T5	257		T16	40
valid_sources[0x45]	89174	1		T4	524		T5	277		T16	13
valid_sources[0x46]	59245	1		T4	600		T5	258		T16	14
valid_sources[0x47]	59637	1		T4	569		T12	1		T5	252
valid_sources[0x48]	60066	1		T4	591		T5	293		T16	12
valid_sources[0x49]	104343	1		T4	726		T5	236		T16	27
valid_sources[0x4a]	61010	1		T4	704		T5	255		T16	5
valid_sources[0x4b]	78744	1		T4	604		T5	305		T16	39
valid_sources[0x4c]	80394	1		T2	1		T4	913		T13	1
valid_sources[0x4d]	58611	1		T4	508		T5	249		T16	58
valid_sources[0x4e]	59501	1		T10	2		T4	662		T5	268
valid_sources[0x4f]	59980	1		T4	563		T5	299		T16	23
valid_sources[0x50]	80073	1		T4	589		T5	266		T16	12
valid_sources[0x51]	72962	1		T4	703		T5	266		T16	9
valid_sources[0x52]	60051	1		T4	944		T5	266		T16	24
valid_sources[0x53]	86451	1		T4	624		T5	260		T16	35
valid_sources[0x54]	106151	1		T4	576		T12	1		T5	235
valid_sources[0x55]	59231	1		T4	615		T5	245		T16	40
valid_sources[0x56]	62135	1		T4	628		T5	234		T16	12
valid_sources[0x57]	152091	1		T4	538		T5	265		T16	6
valid_sources[0x58]	66610	1		T4	684		T5	255		T15	1
valid_sources[0x59]	58638	1		T4	739		T12	1		T5	271
valid_sources[0x5a]	59045	1		T1	1		T4	823		T5	268
valid_sources[0x5b]	58151	1		T1	2		T4	517		T5	261
valid_sources[0x5c]	61560	1		T4	698		T5	240		T16	38
valid_sources[0x5d]	68689	1		T4	614		T5	296		T16	21
valid_sources[0x5e]	57636	1		T4	636		T5	282		T16	10
valid_sources[0x5f]	69791	1		T4	659		T5	264		T16	23
valid_sources[0x60]	58855	1		T4	732		T13	2		T5	247
valid_sources[0x61]	65344	1		T4	835		T5	241		T16	21
valid_sources[0x62]	127200	1		T4	554		T5	263		T16	19
valid_sources[0x63]	63633	1		T1	4		T4	682		T5	250
valid_sources[0x64]	60058	1		T4	741		T5	244		T16	27
valid_sources[0x65]	99925	1		T4	755		T5	263		T14	40152
valid_sources[0x66]	58466	1		T4	557		T5	298		T16	26
valid_sources[0x67]	109950	1		T4	567		T5	277		T16	6
valid_sources[0x68]	59266	1		T1	1		T4	718		T5	270
valid_sources[0x69]	58844	1		T1	3		T4	705		T12	1
valid_sources[0x6a]	58734	1		T10	1		T4	695		T5	238
valid_sources[0x6b]	60378	1		T4	853		T5	268		T16	30
valid_sources[0x6c]	58937	1		T4	635		T5	234		T16	13
valid_sources[0x6d]	60007	1		T4	696		T5	265		T16	5
valid_sources[0x6e]	58224	1		T4	776		T5	269		T16	21
valid_sources[0x6f]	59612	1		T4	579		T5	253		T16	33
valid_sources[0x70]	59872	1		T4	634		T12	1		T5	272
valid_sources[0x71]	59316	1		T4	625		T5	269		T16	32
valid_sources[0x72]	59005	1		T1	1		T4	661		T5	298
valid_sources[0x73]	71267	1		T1	1		T4	652		T5	266
valid_sources[0x74]	154968	1		T4	740		T5	259		T16	28
valid_sources[0x75]	58531	1		T4	593		T5	269		T16	38
valid_sources[0x76]	97282	1		T4	551		T5	269		T16	20
valid_sources[0x77]	59279	1		T4	847		T5	278		T16	45
valid_sources[0x78]	59732	1		T4	609		T5	251		T16	10
valid_sources[0x79]	59634	1		T4	567		T5	241		T16	6
valid_sources[0x7a]	59784	1		T1	2		T4	628		T5	273
valid_sources[0x7b]	104606	1		T4	785		T12	1		T5	250
valid_sources[0x7c]	59607	1		T1	2		T4	523		T5	255
valid_sources[0x7d]	59887	1		T4	650		T5	265		T16	25
valid_sources[0x7e]	73917	1		T1	1		T4	703		T5	289
valid_sources[0x7f]	60355	1		T4	683		T5	297		T16	11
valid_sources[0x80]	141291	1		T4	758		T5	235		T16	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9221358

1

T1

5

T2

1

T3

1

values[0x0]

all_enables

biggest_size

233223

1

T1

13

T10

3

T4

75

values[0x1]

all_enables

biggest_size

220400

1

T1

3

T2

4

T4

85