Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	8937461	1		T1	39		T2	7		T3	9
full_word	9676057	1		T1	21		T2	5		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	18613218	1		T1	60		T2	12		T3	10
auto[TlIntgErrCmd]	106	1		T100	11		T102	5		T106	4
auto[TlIntgErrData]	110	1		T100	6		T102	3		T106	3
auto[TlIntgErrBoth]	84	1		T100	3		T102	2		T106	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	18039083	1		T1	35		T2	3		T3	2
auto[1]	574435	1		T1	25		T2	9		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8817415	1		T1	30		T2	2		T3	1
auto[TlIntgErrNone]	partial	auto[1]	119778	1		T1	9		T2	5		T3	8
auto[TlIntgErrNone]	full_word	auto[0]	9221532	1		T1	5		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	454493	1		T1	16		T2	4		T10	3
auto[TlIntgErrCmd]	partial	auto[0]	50	1		T100	5		T102	3		T106	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T100	6		T102	1		T106	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T110	1		T445	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T102	1		T106	1		T110	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T100	2		T102	2		T106	2
auto[TlIntgErrData]	partial	auto[1]	49	1		T100	1		T102	1		T106	1
auto[TlIntgErrData]	full_word	auto[0]	9	1		T100	1		T107	1		T110	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T100	2		T443	1		T446	1
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T100	3		T106	1		T107	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T102	2		T106	2		T107	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T443	1		T447	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T107	1		T442	2		T275	1