Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.29	94.44	81.34	92.73		97.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	377396895	11575	0	0
ep_in_enable_rd_A	377396895	2793	0	0
ep_out_enable_rd_A	377396895	2866	0	0
in_iso_rd_A	377396895	2601	0	0
intr_enable_rd_A	377396895	3090	0	0
out_iso_rd_A	377396895	2875	0	0
phy_config_rd_A	377396895	1661	0	0
phy_pins_drive_rd_A	377396895	1871	0	0
rxenable_setup_rd_A	377396895	2483	0	0
set_nak_out_rd_A	377396895	2756	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	11575	0	0
T100	39989	3	0	0
T102	19812	4	0	0
T106	18270	1	0	0
T107	50102	5	0	0
T109	5241	5	0	0
T110	15335	4	0	0
T126	5702	304	0	0
T228	9723	640	0	0
T231	7179	488	0	0
T246	5934	15	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2793	0	0
T103	4847	12	0	0
T107	50102	768	0	0
T108	5547	61	0	0
T229	7953	11	0	0
T237	10738	2	0	0
T254	3626	3	0	0
T256	3875	10	0	0
T268	3797	49	0	0
T271	37433	194	0	0
T272	42550	399	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2866	0	0
T103	4847	11	0	0
T107	50102	614	0	0
T108	5547	43	0	0
T109	5241	26	0	0
T229	7953	13	0	0
T238	18240	2	0	0
T254	3626	9	0	0
T268	3797	53	0	0
T271	37433	251	0	0
T272	42550	559	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2601	0	0
T103	4847	9	0	0
T107	50102	400	0	0
T108	5547	45	0	0
T109	5241	34	0	0
T229	7953	50	0	0
T238	18240	1	0	0
T254	3626	7	0	0
T268	3797	43	0	0
T271	37433	200	0	0
T272	42550	473	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	3090	0	0
T103	4847	9	0	0
T107	50102	433	0	0
T108	5547	9	0	0
T109	5241	3	0	0
T136	3314	1	0	0
T137	4019	11	0	0
T229	7953	12	0	0
T268	3797	58	0	0
T273	2290	25	0	0
T274	1542	9	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2875	0	0
T103	4847	11	0	0
T107	50102	437	0	0
T108	5547	53	0	0
T109	5241	8	0	0
T256	3875	103	0	0
T261	7271	54	0	0
T268	3797	59	0	0
T271	37433	208	0	0
T272	42550	575	0	0
T275	28064	215	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	1661	0	0
T103	4847	15	0	0
T107	50102	319	0	0
T108	5547	27	0	0
T109	5241	4	0	0
T229	7953	6	0	0
T254	3626	3	0	0
T256	3875	8	0	0
T268	3797	4	0	0
T271	37433	120	0	0
T272	42550	208	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	1871	0	0
T103	4847	11	0	0
T107	50102	258	0	0
T108	5547	41	0	0
T109	5241	18	0	0
T229	7953	7	0	0
T237	10738	3	0	0
T238	18240	3	0	0
T254	3626	4	0	0
T268	3797	8	0	0
T271	37433	96	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2483	0	0
T103	4847	6	0	0
T107	50102	311	0	0
T108	5547	60	0	0
T109	5241	11	0	0
T229	7953	28	0	0
T256	3875	59	0	0
T261	7271	46	0	0
T268	3797	4	0	0
T271	37433	284	0	0
T272	42550	509	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	2756	0	0
T103	4847	6	0	0
T107	50102	537	0	0
T108	5547	79	0	0
T109	5241	1	0	0
T229	7953	39	0	0
T256	3875	54	0	0
T261	7271	60	0	0
T271	37433	165	0	0
T272	42550	487	0	0
T275	28064	247	0	0