Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_nb_out_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.87 96.85 92.54 87.50 92.45 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe 93.87 96.85 92.54 87.50 92.45 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.87 96.85 92.54 87.50 92.45 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.87 96.85 92.54 87.50 92.45 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12712396.85
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212555192.73
CONT_ASSIGN32611100.00
ALWAYS32933100.00
ALWAYS33733100.00
ALWAYS34677100.00
CONT_ASSIGN36011100.00
ALWAYS36355100.00
ALWAYS37399100.00
ALWAYS39033100.00
ALWAYS40266100.00
CONT_ASSIGN41811100.00
ALWAYS42166100.00
CONT_ASSIGN43511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 0 1
244 1 1
249 1 1
253 1 1
254 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
297 1 1
298 1 1
305 1 1
307 1 1
309 0 1
312 1 1
313 1 1
326 1 1
329 1 1
330 1 1
332 1 1
337 1 1
338 1 1
340 1 1
346 1 1
348 1 1
349 1 1
350 1 1
351 1 1
MISSING_ELSE
354 1 1
355 1 1
MISSING_ELSE
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
368 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
390 1 1
391 1 1
393 1 1
402 1 1
403 1 1
405 1 1
406 1 1
407 1 1
408 1 1
MISSING_ELSE
418 1 1
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
435 1 1


Cond Coverage for Module : usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13412492.54
Logical13412492.54
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT2,T10,T4
1011CoveredT3,T68,T69
1101CoveredT2,T10,T4
1110CoveredT1,T70,T53
1111CoveredT2,T10,T4

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T11
11CoveredT2,T10,T4

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T4,T12
10CoveredT2,T10,T4
11CoveredT4,T12,T13

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T12

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T10
11CoveredT1,T3,T53

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T10
101CoveredT57,T58,T59
110CoveredT1,T2,T10
111CoveredT1,T2,T10

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T12
10CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T12

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T10
101CoveredT1,T3,T53
110CoveredT1,T2,T10
111CoveredT1,T2,T10

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T4,T12
10CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T12

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT1,T70,T53
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT74,T149,T76
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T10
101CoveredT149,T150,T151
110CoveredT1,T2,T10
111CoveredT17,T19,T53

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT53,T74,T76
11CoveredT4,T12,T13

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT53,T152,T153
11CoveredT2,T10,T4

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01CoveredT53,T152,T153
10CoveredT1,T2,T3
11CoveredT2,T10,T4

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T12,T13
10CoveredT2,T10,T4

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T4,T12
10CoveredT53,T30,T154
11CoveredT4,T12,T13

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT2,T10,T4
1Not Covered

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011CoveredT155,T156,T157
101CoveredT2,T10,T4
110CoveredT158,T159,T160
111CoveredT158,T159,T160

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT2,T10,T4
10Not Covered
11CoveredT17,T19,T71

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT2,T10,T4
01CoveredT64,T66,T67
10CoveredT57,T58,T59

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT4,T12,T13
01Not Covered
10Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT2,T10,T4
01Not Covered
10Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT158,T159,T160
01Not Covered
10Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT53,T74,T76
11CoveredT4,T12,T13

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT1,T53,T161
10CoveredT2,T10,T4
11CoveredT2,T10,T4

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT2,T10,T4
01CoveredT2,T10,T4
10CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT2,T10,T4
1CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT53,T162,T36
10CoveredT2,T10,T4
11CoveredT53,T162,T36

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT53,T162,T36
101CoveredT4,T5,T16
110CoveredT1,T2,T3
111CoveredT2,T10,T4

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T10,T4
11CoveredT2,T10,T4

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111CoveredT53,T74,T76
1011CoveredT155,T156,T157
1101Not Covered
1110CoveredT2,T10,T4
1111CoveredT17,T19,T71

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T10,T4

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT1,T161,T158
01CoveredT1,T2,T3
10CoveredT1,T163,T164

FSM Coverage for Module : usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 7 87.50
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 340 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T2,T10,T4
StRcvdDataStart 240 Covered T2,T10,T4
StRcvdIsoDataEnd 253 Covered T158,T159,T160
StRcvdOut 226 Covered T2,T10,T4


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 226 Covered T2,T10,T4
StRcvdDataEnd->StIdle 340 Covered T2,T10,T4
StRcvdDataStart->StIdle 340 Covered T17,T19,T57
StRcvdDataStart->StRcvdDataEnd 266 Covered T2,T10,T4
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T158,T159,T160
StRcvdIsoDataEnd->StIdle 340 Covered T158,T159,T160
StRcvdOut->StIdle 340 Not Covered
StRcvdOut->StRcvdDataStart 240 Covered T2,T10,T4



Branch Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 53 49 92.45
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 18 14 77.78
IF 329 2 2 100.00
IF 337 3 3 100.00
IF 348 3 3 100.00
IF 354 2 2 100.00
IF 363 3 3 100.00
IF 373 3 3 100.00
IF 390 2 2 100.00
IF 402 4 4 100.00
IF 421 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T70,T53


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T12,T13
0 0 1 Covered T2,T10,T4
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T10
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 292 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 307 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T2,T10,T4
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T2,T10,T4
StRcvdOut - 0 1 - - - - - - - - - Not Covered
StRcvdOut - 0 0 - - - - - - - - - Covered T2,T10,T4
StRcvdDataStart - - - 1 - - - - - - - - Covered T158,T159,T160
StRcvdDataStart - - - 0 1 - - - - - - - Covered T17,T19,T71
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T57,T58,T59
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T2,T10,T4
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T2,T10,T4
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T4,T12,T13
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T53,T165,T166
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T53,T162,T36
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T2,T10,T4
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T158,T159,T160
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 329 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((!rst_ni)) -2-: 340 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if ((setup_token_received && ep_active)) -2-: 350 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T4,T12,T13
0 1 Covered T2,T10,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 354 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T17,T19,T82
0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((!rst_ni)) -2-: 365 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 378 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T10,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 if ((!rst_ni)) -2-: 405 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 407 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T53,T162,T36
0 0 0 Covered T2,T10,T4


LineNo. Expression -1-: 421 if ((!rst_ni)) -2-: 424 if ((out_xact_state == StRcvdOut)) -3-: 426 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T10,T4
0 0 1 Covered T2,T10,T4
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 375709729 375490852 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375709729 375490852 0 0
T1 31351 31285 0 0
T2 8881 8794 0 0
T3 8464 8380 0 0
T4 519576 519482 0 0
T5 140222 140131 0 0
T10 7354 7264 0 0
T11 9582 9482 0 0
T12 9232 9162 0 0
T13 7298 7220 0 0
T14 96386 96286 0 0