Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9525126	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	10107789	1		T1	5		T2	6		T3	12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19041668	1		T1	2		T2	2		T3	30
values[0x0]	295612	1		T1	3		T2	5		T3	10
values[0x1]	295635	1		T1	4		T2	3		T3	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7574865	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	12058050	1		T1	8		T2	6		T3	21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	92465	1		T6	186		T35	63		T105	6
valid_sources[0x01]	62030	1		T6	196		T35	95		T105	4
valid_sources[0x02]	61788	1		T6	179		T35	96		T105	4
valid_sources[0x03]	60883	1		T6	193		T35	81		T105	2
valid_sources[0x04]	158192	1		T6	194		T35	84		T105	4
valid_sources[0x05]	60469	1		T6	169		T35	93		T105	2
valid_sources[0x06]	63140	1		T1	2		T2	3		T6	187
valid_sources[0x07]	194443	1		T30	1		T6	171		T35	114
valid_sources[0x08]	221054	1		T6	215		T35	83		T105	2
valid_sources[0x09]	62139	1		T32	3		T6	186		T35	101
valid_sources[0x0a]	99602	1		T6	161		T35	56		T105	4
valid_sources[0x0b]	62059	1		T6	182		T35	100		T105	3
valid_sources[0x0c]	64093	1		T6	207		T35	68		T105	2
valid_sources[0x0d]	61598	1		T6	204		T34	1		T35	93
valid_sources[0x0e]	63275	1		T6	190		T35	61		T105	4
valid_sources[0x0f]	133641	1		T6	194		T35	75		T105	2
valid_sources[0x10]	70453	1		T6	203		T35	81		T105	3
valid_sources[0x11]	64162	1		T6	197		T35	58		T105	4
valid_sources[0x12]	74569	1		T6	184		T35	106		T25	35
valid_sources[0x13]	61660	1		T6	212		T35	81		T105	5
valid_sources[0x14]	64167	1		T6	182		T35	88		T105	4
valid_sources[0x15]	73835	1		T2	2		T6	193		T35	128
valid_sources[0x16]	120921	1		T6	179		T34	2		T109	1
valid_sources[0x17]	62987	1		T6	199		T35	83		T105	2
valid_sources[0x18]	61312	1		T6	208		T35	84		T105	3
valid_sources[0x19]	63432	1		T6	173		T35	65		T105	4
valid_sources[0x1a]	61549	1		T6	181		T35	80		T105	2
valid_sources[0x1b]	79874	1		T6	178		T35	121		T7	1
valid_sources[0x1c]	168069	1		T6	166		T35	75		T7	1
valid_sources[0x1d]	169120	1		T6	184		T35	86		T105	2
valid_sources[0x1e]	60610	1		T6	208		T35	101		T105	4
valid_sources[0x1f]	79283	1		T6	207		T35	79		T105	3
valid_sources[0x20]	60778	1		T6	164		T35	107		T105	2
valid_sources[0x21]	62029	1		T6	168		T35	72		T105	4
valid_sources[0x22]	61652	1		T6	196		T35	87		T105	3
valid_sources[0x23]	61120	1		T6	217		T35	84		T105	2
valid_sources[0x24]	73937	1		T6	193		T35	92		T105	5
valid_sources[0x25]	62168	1		T6	204		T35	107		T105	1
valid_sources[0x26]	164664	1		T6	197		T35	103		T105	4
valid_sources[0x27]	143425	1		T6	180		T35	138		T105	3
valid_sources[0x28]	62599	1		T6	191		T109	2		T35	132
valid_sources[0x29]	61936	1		T6	207		T35	65		T105	3
valid_sources[0x2a]	86127	1		T6	189		T35	73		T105	3
valid_sources[0x2b]	61277	1		T1	2		T6	171		T109	1
valid_sources[0x2c]	60904	1		T6	202		T35	78		T105	1
valid_sources[0x2d]	62986	1		T6	189		T35	79		T18	2
valid_sources[0x2e]	61831	1		T30	2		T6	183		T35	75
valid_sources[0x2f]	185835	1		T5	17362		T6	196		T35	92
valid_sources[0x30]	61854	1		T3	2		T30	5		T6	174
valid_sources[0x31]	62223	1		T30	19		T6	200		T35	94
valid_sources[0x32]	61641	1		T2	2		T6	188		T35	102
valid_sources[0x33]	76782	1		T6	186		T35	99		T105	5
valid_sources[0x34]	79053	1		T30	4		T6	176		T35	87
valid_sources[0x35]	59902	1		T6	198		T35	60		T105	3
valid_sources[0x36]	64355	1		T6	183		T35	90		T105	2
valid_sources[0x37]	60294	1		T30	2		T6	176		T35	68
valid_sources[0x38]	61320	1		T30	3		T6	188		T34	1
valid_sources[0x39]	61265	1		T6	165		T35	131		T105	2
valid_sources[0x3a]	102482	1		T6	189		T34	5		T35	73
valid_sources[0x3b]	61635	1		T6	184		T35	90		T105	2
valid_sources[0x3c]	86543	1		T6	193		T35	104		T105	6
valid_sources[0x3d]	75862	1		T6	190		T35	97		T105	2
valid_sources[0x3e]	62761	1		T6	193		T35	108		T105	2
valid_sources[0x3f]	60828	1		T3	2		T6	195		T35	74
valid_sources[0x40]	61068	1		T6	191		T35	73		T105	5
valid_sources[0x41]	83479	1		T32	4		T6	203		T35	103
valid_sources[0x42]	61024	1		T6	163		T35	128		T105	2
valid_sources[0x43]	123096	1		T6	209		T35	67		T105	4
valid_sources[0x44]	62600	1		T6	199		T35	85		T105	2
valid_sources[0x45]	61011	1		T31	1		T6	204		T35	84
valid_sources[0x46]	60073	1		T6	188		T35	92		T105	1
valid_sources[0x47]	61473	1		T6	184		T35	99		T105	3
valid_sources[0x48]	62920	1		T6	181		T35	161		T105	2
valid_sources[0x49]	60861	1		T3	5		T6	199		T35	109
valid_sources[0x4a]	62482	1		T30	15		T6	180		T35	115
valid_sources[0x4b]	75542	1		T30	4		T6	202		T35	64
valid_sources[0x4c]	82599	1		T6	158		T34	1		T35	108
valid_sources[0x4d]	68295	1		T6	183		T35	85		T250	1
valid_sources[0x4e]	61583	1		T6	202		T35	102		T105	3
valid_sources[0x4f]	62829	1		T33	11		T6	175		T35	89
valid_sources[0x50]	62265	1		T6	200		T35	142		T105	1
valid_sources[0x51]	63796	1		T6	188		T35	108		T105	2
valid_sources[0x52]	103957	1		T6	179		T34	3		T35	91
valid_sources[0x53]	109287	1		T3	1		T6	200		T35	134
valid_sources[0x54]	62604	1		T30	6		T6	193		T35	89
valid_sources[0x55]	95651	1		T6	165		T35	76		T105	5
valid_sources[0x56]	60756	1		T6	206		T35	106		T105	2
valid_sources[0x57]	60852	1		T6	182		T35	80		T105	5
valid_sources[0x58]	74131	1		T6	205		T35	71		T105	3
valid_sources[0x59]	91320	1		T6	174		T35	70		T105	1
valid_sources[0x5a]	63690	1		T6	200		T35	76		T105	3
valid_sources[0x5b]	65091	1		T6	217		T35	76		T105	5
valid_sources[0x5c]	61532	1		T6	162		T35	84		T25	33
valid_sources[0x5d]	62161	1		T30	5		T6	174		T35	118
valid_sources[0x5e]	77514	1		T3	1		T6	195		T34	1
valid_sources[0x5f]	61062	1		T1	1		T6	214		T35	91
valid_sources[0x60]	83366	1		T6	180		T35	85		T105	3
valid_sources[0x61]	60992	1		T30	12		T6	173		T35	72
valid_sources[0x62]	138040	1		T3	1		T6	186		T35	72
valid_sources[0x63]	61504	1		T30	4		T6	190		T35	65
valid_sources[0x64]	155411	1		T6	183		T35	91		T105	6
valid_sources[0x65]	61999	1		T6	182		T35	83		T105	3
valid_sources[0x66]	132985	1		T6	194		T35	100		T7	1
valid_sources[0x67]	61462	1		T6	192		T35	85		T105	2
valid_sources[0x68]	61386	1		T6	178		T35	89		T105	4
valid_sources[0x69]	62968	1		T6	163		T35	77		T105	5
valid_sources[0x6a]	62123	1		T6	183		T35	115		T7	7
valid_sources[0x6b]	69604	1		T6	173		T35	68		T105	1
valid_sources[0x6c]	61434	1		T6	185		T35	71		T105	2
valid_sources[0x6d]	91988	1		T6	197		T35	70		T105	3
valid_sources[0x6e]	60681	1		T30	5		T6	217		T35	76
valid_sources[0x6f]	60624	1		T6	182		T35	93		T25	56
valid_sources[0x70]	61100	1		T6	204		T35	63		T105	6
valid_sources[0x71]	92051	1		T6	166		T35	84		T105	1
valid_sources[0x72]	63235	1		T6	170		T35	89		T105	4
valid_sources[0x73]	78474	1		T30	3		T6	191		T35	105
valid_sources[0x74]	77016	1		T6	176		T35	110		T7	2
valid_sources[0x75]	72202	1		T6	171		T109	1		T35	91
valid_sources[0x76]	64759	1		T6	198		T103	5		T35	66
valid_sources[0x77]	59712	1		T6	212		T35	97		T105	1
valid_sources[0x78]	61612	1		T31	8		T6	202		T35	82
valid_sources[0x79]	59884	1		T6	203		T36	11		T35	99
valid_sources[0x7a]	60959	1		T6	219		T35	98		T105	2
valid_sources[0x7b]	185242	1		T30	2		T6	220		T35	64
valid_sources[0x7c]	61604	1		T6	194		T35	76		T105	1
valid_sources[0x7d]	75305	1		T1	1		T30	4		T6	213
valid_sources[0x7e]	123763	1		T3	2		T6	167		T35	91
valid_sources[0x7f]	71260	1		T6	167		T35	104		T105	3
valid_sources[0x80]	60640	1		T6	173		T35	115		T105	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

9627913

1

T1

2

T2

1

T3

5

values[0x0]

all_enables

biggest_size

248063

1

T1

2

T2

3

T3

6

values[0x1]

all_enables

biggest_size

231813

1

T1

1

T2

2

T3

1