Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	9537565	1		T1	4		T2	4		T3	36
full_word	10108616	1		T1	5		T2	6		T3	12

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	19645881	1		T1	9		T2	10		T3	48
auto[TlIntgErrCmd]	104	1		T206	3		T232	3		T235	4
auto[TlIntgErrData]	95	1		T232	2		T235	4		T237	6
auto[TlIntgErrBoth]	101	1		T206	7		T232	5		T235	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	19043275	1		T1	2		T2	2		T3	30
auto[1]	602906	1		T1	7		T2	8		T3	18

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9415074	1		T2	1		T3	25		T30	43
auto[TlIntgErrNone]	partial	auto[1]	122219	1		T1	4		T2	3		T3	11
auto[TlIntgErrNone]	full_word	auto[0]	9628066	1		T1	2		T2	1		T3	5
auto[TlIntgErrNone]	full_word	auto[1]	480522	1		T1	3		T2	5		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T206	1		T232	3		T237	4
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T206	2		T235	4		T237	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T330	1		T333	2		T334	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T237	1		T330	1		T333	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T232	1		T235	2		T237	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T232	1		T235	2		T237	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T237	1		T335	1		T336	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T337	1		T330	1		T331	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T206	1		T232	3		T235	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T206	6		T232	1		T235	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T330	1		T338	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T232	1		T329	1		T337	1