Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	558105364	10224	0	0
ep_in_enable_rd_A	558105364	2569	0	0
ep_out_enable_rd_A	558105364	2630	0	0
in_iso_rd_A	558105364	2610	0	0
intr_enable_rd_A	558105364	3877	0	0
out_iso_rd_A	558105364	2599	0	0
phy_config_rd_A	558105364	2000	0	0
phy_pins_drive_rd_A	558105364	2279	0	0
rxenable_setup_rd_A	558105364	2705	0	0
set_nak_out_rd_A	558105364	2720	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	10224	0	0
T206	12400	4	0	0
T207	8297	19	0	0
T208	2373	3	0	0
T230	5200	6	0	0
T231	5642	323	0	0
T232	37562	5	0	0
T235	15906	2	0	0
T236	3730	488	0	0
T237	31184	5	0	0
T251	5111	13	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2569	0	0
T207	8297	57	0	0
T230	5200	33	0	0
T244	9932	2	0	0
T252	5072	23	0	0
T271	15193	9	0	0
T278	5001	8	0	0
T279	10872	87	0	0
T285	16174	3	0	0
T293	9670	49	0	0
T294	9837	29	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2630	0	0
T207	8297	59	0	0
T230	5200	26	0	0
T252	5072	5	0	0
T271	15193	5	0	0
T278	5001	8	0	0
T279	10872	72	0	0
T285	16174	26	0	0
T293	9670	19	0	0
T294	9837	54	0	0
T295	7056	45	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2610	0	0
T207	8297	79	0	0
T230	5200	16	0	0
T252	5072	13	0	0
T271	15193	8	0	0
T278	5001	3	0	0
T279	10872	79	0	0
T285	16174	14	0	0
T293	9670	25	0	0
T294	9837	28	0	0
T295	7056	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	3877	0	0
T207	8297	19	0	0
T213	3366	13	0	0
T230	5200	39	0	0
T252	5072	42	0	0
T271	15193	8	0	0
T285	16174	7	0	0
T296	2982	14	0	0
T297	2007	15	0	0
T298	2780	25	0	0
T299	2395	15	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2599	0	0
T207	8297	10	0	0
T252	5072	7	0	0
T271	15193	2	0	0
T278	5001	1	0	0
T279	10872	82	0	0
T285	16174	41	0	0
T293	9670	13	0	0
T294	9837	9	0	0
T295	7056	54	0	0
T300	6625	61	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2000	0	0
T207	8297	39	0	0
T230	5200	20	0	0
T252	5072	16	0	0
T271	15193	6	0	0
T278	5001	15	0	0
T279	10872	94	0	0
T285	16174	5	0	0
T293	9670	3	0	0
T294	9837	6	0	0
T295	7056	22	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2279	0	0
T207	8297	24	0	0
T244	9932	6	0	0
T252	5072	16	0	0
T271	15193	5	0	0
T278	5001	9	0	0
T279	10872	96	0	0
T285	16174	15	0	0
T293	9670	15	0	0
T294	9837	11	0	0
T295	7056	35	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2705	0	0
T207	8297	54	0	0
T230	5200	12	0	0
T245	10418	6	0	0
T252	5072	23	0	0
T271	15193	14	0	0
T278	5001	10	0	0
T279	10872	131	0	0
T285	16174	8	0	0
T293	9670	12	0	0
T294	9837	49	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	558105364	2720	0	0
T207	8297	93	0	0
T230	5200	1	0	0
T271	15193	4	0	0
T278	5001	15	0	0
T279	10872	84	0	0
T285	16174	9	0	0
T293	9670	41	0	0
T294	9837	24	0	0
T295	7056	55	0	0
T300	6625	49	0	0