Module Definition
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Module : usb_fs_nb_in_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.68 97.50 93.91 75.00 92.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe 91.68 97.50 93.91 75.00 92.00 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_in_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.68 97.50 93.91 75.00 92.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.68 97.50 93.91 75.00 92.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
TOTAL12011797.50
CONT_ASSIGN11811100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN16011100.00
CONT_ASSIGN16111100.00
CONT_ASSIGN16811100.00
CONT_ASSIGN16911100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17811100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
ALWAYS199494693.88
ALWAYS30333100.00
ALWAYS31133100.00
ALWAYS31988100.00
ALWAYS33266100.00
ALWAYS34499100.00
ALWAYS36177100.00
CONT_ASSIGN37511100.00
ALWAYS37855100.00
ALWAYS38855100.00
CONT_ASSIGN40511100.00
CONT_ASSIGN41211100.00
ALWAYS42233100.00
CONT_ASSIGN42511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
118 1 1
132 1 1
133 1 1
135 1 1
141 1 1
145 1 1
149 1 1
154 1 1
160 1 1
161 1 1
168 1 1
169 1 1
172 1 1
178 1 1
180 1 1
186 1 1
188 1 1
189 1 1
199 1 1
200 1 1
201 1 1
202 1 1
203 1 1
204 1 1
205 1 1
207 1 1
208 1 1
211 1 1
216 1 1
218 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
232 1 1
233 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
245 0 1
247 1 1
251 1 1
256 1 1
257 1 1
MISSING_ELSE
265 1 1
267 1 1
268 1 1
269 1 1
270 1 1
271 1 1
273 1 1
278 1 1
279 1 1
280 1 1
281 1 1
283 0 1
284 0 1
285 1 1
287 1 1
288 1 1
290 1 1
303 1 1
304 1 1
306 1 1
311 1 1
312 1 1
314 1 1
319 1 1
320 1 1
321 1 1
322 1 1
323 1 1
324 1 1
326 1 1
327 1 1
332 1 1
333 1 1
335 1 1
336 1 1
337 1 1
338 1 1
MISSING_ELSE
344 1 1
345 1 1
346 1 1
347 1 1
349 1 1
350 1 1
351 1 1
352 1 1
354 1 1
361 1 1
363 1 1
364 1 1
365 1 1
366 1 1
MISSING_ELSE
369 1 1
370 1 1
MISSING_ELSE
375 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
388 1 1
389 1 1
391 1 1
392 1 1
394 1 1
405 1 1
412 1 1
422 2 2
423 1 1
425 1 1


Cond Coverage for Module : usb_fs_nb_in_pe
TotalCoveredPercent
Conditions11510893.91
Logical11510893.91
Non-Logical00
Event00

 LINE       135
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T3,T30
1011CoveredT62,T76,T73
1101CoveredT3,T30,T32
1110CoveredT2,T7,T18
1111CoveredT1,T3,T30

 LINE       135
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       135
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       141
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT3,T4,T5
10CoveredT1,T30,T31
11CoveredT3,T4,T5

 LINE       141
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T4,T5

 LINE       145
 EXPRESSION (token_received && (rx_pid == UsbPidIn))
             -------1------    ----------2---------
-1--2-StatusTests
01CoveredT1,T30,T31
10CoveredT3,T30,T32
11CoveredT1,T30,T31

 LINE       145
 SUB-EXPRESSION (rx_pid == UsbPidIn)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T30,T31

 LINE       149
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidAck))
             ------1-----    -------2------    ----------3----------
-1--2--3-StatusTests
011CoveredT30,T32,T4
101CoveredT77,T82
110CoveredT1,T2,T3
111CoveredT30,T32,T4

 LINE       149
 SUB-EXPRESSION (rx_pid == UsbPidAck)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       154
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid == UsbPidNak))
             ------1-----    -------2------    ----------3----------
-1--2--3-StatusTests
011CoveredT19,T83,T84
101CoveredT62,T80
110CoveredT1,T2,T3
111CoveredT19,T84,T85

 LINE       154
 SUB-EXPRESSION (rx_pid == UsbPidNak)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       161
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT35,T18,T56
1CoveredT1,T2,T3

 LINE       172
 EXPRESSION (in_ep_enabled_i[in_ep_index_d] & ep_in_hw)
             ---------------1--------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T87,T88
11CoveredT1,T30,T31

 LINE       178
 EXPRESSION (has_data_q & ((~in_ep_data_done_i[in_ep_index])))
             -----1----   -----------------2-----------------
-1--2-StatusTests
01CoveredT64,T88,T89
10CoveredT1,T30,T31
11CoveredT30,T32,T4

 LINE       180
 EXPRESSION ((logic'((in_xact_state == StSendData))) & more_data_to_send)
             -------------------1-------------------   --------2--------
-1--2-StatusTests
01CoveredT30,T32,T4
10CoveredT30,T32,T4
11CoveredT30,T32,T4

 LINE       186
 EXPRESSION (((in_xact_state == StIdle) || (in_xact_state == StWaitAck)) && in_token_received)
             -----------------------------1-----------------------------    --------2--------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T30,T31

 LINE       186
 SUB-EXPRESSION ((in_xact_state == StIdle) || (in_xact_state == StWaitAck))
                 ------------1------------    --------------2-------------
-1--2-StatusTests
00CoveredT1,T30,T31
01CoveredT30,T32,T4
10CoveredT1,T2,T3

 LINE       186
 SUB-EXPRESSION (in_xact_state == StIdle)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       186
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       188
 EXPRESSION (in_starting & ep_active)
             -----1-----   ----2----
-1--2-StatusTests
01CoveredT1,T30,T31
10CoveredT88,T90,T91
11CoveredT1,T30,T31

 LINE       207
 EXPRESSION (ep_active && in_token_received)
             ----1----    --------2--------
-1--2-StatusTests
01CoveredT88,T90,T91
10CoveredT1,T30,T31
11CoveredT1,T30,T31

 LINE       239
 EXPRESSION (((!more_data_to_send)) || (((&in_ep_get_addr_o)) && tx_data_get_i))
             -----------1----------    --------------------2-------------------
-1--2-StatusTests
00CoveredT30,T32,T4
01CoveredT6,T35,T92
10CoveredT30,T32,T4

 LINE       239
 SUB-EXPRESSION (((&in_ep_get_addr_o)) && tx_data_get_i)
                 ----------1----------    ------2------
-1--2-StatusTests
01CoveredT30,T32,T4
10CoveredT5,T6,T35
11CoveredT6,T35,T92

 LINE       269
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT30,T32,T4
1CoveredT25,T57,T93

 LINE       283
 EXPRESSION (ep_active ? StRcvdIn : StIdle)
             ----1----
-1-StatusTests
0Not Covered
1Not Covered

 LINE       322
 EXPRESSION (link_reset_i || ((!link_active_i)))
             ------1-----    ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       335
 EXPRESSION (in_xact_state == StIdle)
            ------------1------------
-1-StatusTests
0CoveredT1,T30,T31
1CoveredT1,T2,T3

 LINE       337
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT30,T32,T4
11CoveredT30,T32,T4

 LINE       337
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T30,T31
1CoveredT30,T32,T4

 LINE       363
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T30,T31
10CoveredT3,T23,T94
11CoveredT4,T5,T6

 LINE       365
 EXPRESSION ((in_xact_state == StWaitAck) && ack_received)
             --------------1-------------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT30,T32,T4
11CoveredT30,T32,T4

 LINE       365
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       391
 EXPRESSION ((in_xact_state == StSendData) && tx_data_get_i)
             --------------1--------------    ------2------
-1--2-StatusTests
01Not Covered
10CoveredT30,T32,T4
11CoveredT30,T32,T4

 LINE       391
 SUB-EXPRESSION (in_xact_state == StSendData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       405
 EXPRESSION (((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))) & rollback_in_xact)
             -----------------------------------------------------1----------------------------------------------------   --------2-------
-1--2-StatusTests
01CoveredT19,T84,T85
10CoveredT30,T32,T4
11CoveredT19,T25,T57

 LINE       405
 SUB-EXPRESSION ((in_xact_state == StWaitAckStart) || ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received))))
                 ----------------1----------------    ---------------------------------2---------------------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT30,T32,T4
10CoveredT30,T32,T4

 LINE       405
 SUB-EXPRESSION (in_xact_state == StWaitAckStart)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       405
 SUB-EXPRESSION ((in_xact_state == StWaitAck) && rx_pkt_end_i && ((!nak_received)))
                 --------------1-------------    ------2-----    --------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT30,T32,T4
110CoveredT19,T84,T85
111CoveredT30,T32,T4

 LINE       405
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       412
 EXPRESSION ((in_xact_state == StWaitAck) && nak_received)
             --------------1-------------    ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT30,T32,T4
11CoveredT19,T84,T85

 LINE       412
 SUB-EXPRESSION (in_xact_state == StWaitAck)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT30,T32,T4

 LINE       423
 EXPRESSION (in_starting & (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0))
             -----1-----   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T30,T31
11CoveredT4,T5,T6

 LINE       423
 SUB-EXPRESSION (ep_in_hw ? ((!in_ep_has_data_i[in_ep_index_d])) : 1'b0)
                 ----1---
-1-StatusTests
0CoveredT35,T18,T56
1CoveredT1,T2,T3

FSM Coverage for Module : usb_fs_nb_in_pe
Summary for FSM :: in_xact_state
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 12 9 75.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: in_xact_state
states   Line No.   Covered   Tests   
StIdle 323 Covered T1,T2,T3
StRcvdIn 208 Covered T1,T30,T31
StSendData 223 Covered T30,T32,T4
StWaitAck 268 Covered T30,T32,T4
StWaitAckStart 245 Covered T30,T32,T4
StWaitTxEnd 247 Covered T30,T32,T4


transitions   Line No.   Covered   Tests   
StIdle->StRcvdIn 208 Covered T1,T30,T31
StRcvdIn->StIdle 323 Covered T1,T31,T4
StRcvdIn->StSendData 223 Covered T30,T32,T4
StSendData->StIdle 323 Covered T95,T96,T64
StSendData->StWaitAckStart 245 Not Covered
StSendData->StWaitTxEnd 247 Covered T30,T32,T4
StWaitAck->StIdle 323 Covered T30,T32,T4
StWaitAck->StRcvdIn 283 Not Covered
StWaitAckStart->StIdle 323 Covered T25,T57,T93
StWaitAckStart->StWaitAck 268 Covered T30,T32,T4
StWaitTxEnd->StIdle 323 Not Covered
StWaitTxEnd->StWaitAckStart 257 Covered T30,T32,T4



Branch Coverage for Module : usb_fs_nb_in_pe
Line No.TotalCoveredPercent
Branches 50 46 92.00
TERNARY 161 2 2 100.00
CASE 205 21 17 80.95
IF 303 2 2 100.00
IF 311 2 2 100.00
IF 319 3 3 100.00
IF 332 4 4 100.00
IF 344 3 3 100.00
IF 363 3 3 100.00
IF 369 2 2 100.00
IF 378 3 3 100.00
IF 388 3 3 100.00
IF 422 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_in_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 161 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T35,T18,T56


LineNo. Expression -1-: 205 case (in_xact_state) -2-: 207 if ((ep_active && in_token_received)) -3-: 218 if (in_ep_iso_i[in_ep_index]) -4-: 225 if (in_ep_stall_i[in_ep_index]) -5-: 228 if (has_data_q) -6-: 239 if (((!more_data_to_send) || ((&in_ep_get_addr_o) && tx_data_get_i))) -7-: 240 if (in_ep_iso_i[in_ep_index]) -8-: 244 if (tx_pkt_end_i) -9-: 256 if (tx_pkt_end_i) -10-: 267 if (rx_pkt_start_i) -11-: 269 if ((timeout_cntdown_q == '0)) -12-: 278 if (ack_received) -13-: 281 if (in_token_received) -14-: 283 (ep_active) ? -15-: 285 if (rx_pkt_end_i)

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15-StatusTests
StIdle 1 - - - - - - - - - - - - - Covered T1,T30,T31
StIdle 0 - - - - - - - - - - - - - Covered T1,T2,T3
StRcvdIn - 1 - - - - - - - - - - - - Covered T95,T96,T64
StRcvdIn - 0 1 - - - - - - - - - - - Covered T1,T31,T97
StRcvdIn - 0 0 1 - - - - - - - - - - Covered T30,T32,T4
StRcvdIn - 0 0 0 - - - - - - - - - - Covered T4,T5,T6
StSendData - - - - 1 1 - - - - - - - - Covered T95,T96,T64
StSendData - - - - 1 0 1 - - - - - - - Not Covered
StSendData - - - - 1 0 0 - - - - - - - Covered T30,T32,T4
StSendData - - - - 0 - - - - - - - - - Covered T30,T32,T4
StWaitTxEnd - - - - - - - 1 - - - - - - Covered T30,T32,T4
StWaitTxEnd - - - - - - - 0 - - - - - - Covered T30,T32,T4
StWaitAckStart - - - - - - - - 1 - - - - - Covered T30,T32,T4
StWaitAckStart - - - - - - - - 0 1 - - - - Covered T25,T57,T93
StWaitAckStart - - - - - - - - 0 0 - - - - Covered T30,T32,T4
StWaitAck - - - - - - - - - - 1 - - - Covered T30,T32,T4
StWaitAck - - - - - - - - - - 0 1 1 - Not Covered
StWaitAck - - - - - - - - - - 0 1 0 - Not Covered
StWaitAck - - - - - - - - - - 0 0 - 1 Covered T19,T83,T84
StWaitAck - - - - - - - - - - 0 0 - 0 Covered T30,T32,T4
default - - - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 303 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 311 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 319 if ((!rst_ni)) -2-: 322 if ((link_reset_i || (!link_active_i)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 332 if ((!rst_ni)) -2-: 335 if ((in_xact_state == StIdle)) -3-: 337 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T30,T32,T4
0 0 0 Covered T1,T30,T31


LineNo. Expression -1-: 344 if ((!rst_ni)) -2-: 349 if (in_token_received)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T30,T31
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((setup_token_received && ep_active)) -2-: 365 if (((in_xact_state == StWaitAck) && ack_received))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T30,T32,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 369 if (in_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T19,T84,T85
0 Covered T1,T2,T3


LineNo. Expression -1-: 378 if ((!rst_ni)) -2-: 380 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 388 if ((!rst_ni)) -2-: 391 if (((in_xact_state == StSendData) && tx_data_get_i))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T30,T32,T4
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 422 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_in_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
InXactStateValid_A 556377754 556144838 0 0


InXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 556377754 556144838 0 0
T1 6674 6595 0 0
T2 7268 7176 0 0
T3 12876 12788 0 0
T4 191530 191462 0 0
T5 170628 170564 0 0
T6 105937 105873 0 0
T30 38419 38321 0 0
T31 7858 7801 0 0
T32 10174 10123 0 0
T33 12313 12226 0 0