Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	365	1		T2	8		T14	5		T7	5
all_values[1]	365	1		T2	8		T14	5		T7	5
all_values[2]	365	1		T2	8		T14	5		T7	5
all_values[3]	365	1		T2	8		T14	5		T7	5
all_values[4]	365	1		T2	8		T14	5		T7	5
all_values[5]	365	1		T2	8		T14	5		T7	5
all_values[6]	365	1		T2	8		T14	5		T7	5
all_values[7]	365	1		T2	8		T14	5		T7	5
all_values[8]	365	1		T2	8		T14	5		T7	5
all_values[9]	365	1		T2	8		T14	5		T7	5
all_values[10]	365	1		T2	8		T14	5		T7	5
all_values[11]	365	1		T2	8		T14	5		T7	5
all_values[12]	365	1		T2	8		T14	5		T7	5
all_values[13]	365	1		T2	8		T14	5		T7	5
all_values[14]	365	1		T2	8		T14	5		T7	5
all_values[15]	365	1		T2	8		T14	5		T7	5
all_values[16]	365	1		T2	8		T14	5		T7	5
all_values[17]	365	1		T2	8		T14	5		T7	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	8781	1		T2	198		T14	112		T7	116
auto[1]	2899	1		T2	58		T14	48		T7	44

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9347	1		T2	189		T14	125		T7	121
auto[1]	2333	1		T2	67		T14	35		T7	39

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	147	1		T2	3		T14	1		T7	4
all_values[0]	auto[0]	auto[1]	45	1		T2	3		T14	1		T15	2
all_values[0]	auto[1]	auto[0]	111	1		T14	2		T15	3		T16	3
all_values[0]	auto[1]	auto[1]	62	1		T2	2		T14	1		T7	1
all_values[1]	auto[0]	auto[0]	150	1		T2	3		T15	2		T16	3
all_values[1]	auto[0]	auto[1]	61	1		T15	3		T16	1		T36	1
all_values[1]	auto[1]	auto[0]	103	1		T2	3		T14	3		T7	3
all_values[1]	auto[1]	auto[1]	51	1		T2	2		T14	2		T7	2
all_values[2]	auto[0]	auto[0]	106	1		T2	2		T14	1		T15	2
all_values[2]	auto[0]	auto[1]	94	1		T2	6		T7	1		T15	1
all_values[2]	auto[1]	auto[0]	81	1		T14	4		T7	2		T15	1
all_values[2]	auto[1]	auto[1]	84	1		T7	2		T15	4		T16	1
all_values[3]	auto[0]	auto[0]	136	1		T2	1		T7	2		T15	1
all_values[3]	auto[0]	auto[1]	64	1		T2	5		T15	2		T36	2
all_values[3]	auto[1]	auto[0]	100	1		T2	1		T14	1		T7	3
all_values[3]	auto[1]	auto[1]	65	1		T2	1		T14	4		T15	2
all_values[4]	auto[0]	auto[0]	141	1		T14	1		T38	1		T39	4
all_values[4]	auto[0]	auto[1]	64	1		T2	1		T14	3		T7	1
all_values[4]	auto[1]	auto[0]	112	1		T2	5		T14	1		T7	3
all_values[4]	auto[1]	auto[1]	48	1		T2	2		T7	1		T16	2
all_values[5]	auto[0]	auto[0]	119	1		T2	2		T14	3		T15	2
all_values[5]	auto[0]	auto[1]	64	1		T2	4		T7	2		T15	1
all_values[5]	auto[1]	auto[0]	100	1		T2	2		T14	2		T7	1
all_values[5]	auto[1]	auto[1]	82	1		T7	2		T15	3		T16	3
all_values[6]	auto[0]	auto[0]	136	1		T2	2		T14	2		T7	4
all_values[6]	auto[0]	auto[1]	69	1		T2	2		T14	3		T7	1
all_values[6]	auto[1]	auto[0]	89	1		T2	4		T15	1		T16	2
all_values[6]	auto[1]	auto[1]	71	1		T15	2		T16	2		T39	1
all_values[7]	auto[0]	auto[0]	141	1		T2	1		T15	4		T16	3
all_values[7]	auto[0]	auto[1]	57	1		T7	2		T15	3		T16	1
all_values[7]	auto[1]	auto[0]	115	1		T2	3		T14	4		T7	3
all_values[7]	auto[1]	auto[1]	52	1		T2	4		T14	1		T41	3
all_values[8]	auto[0]	auto[0]	153	1		T2	4		T14	2		T7	3
all_values[8]	auto[0]	auto[1]	58	1		T2	3		T14	3		T7	1
all_values[8]	auto[1]	auto[0]	102	1		T2	1		T7	1		T15	5
all_values[8]	auto[1]	auto[1]	52	1		T15	1		T16	1		T36	2
all_values[9]	auto[0]	auto[0]	137	1		T2	4		T14	1		T15	1
all_values[9]	auto[0]	auto[1]	75	1		T2	1		T14	1		T7	2
all_values[9]	auto[1]	auto[0]	95	1		T2	1		T14	3		T7	1
all_values[9]	auto[1]	auto[1]	58	1		T2	2		T7	2		T15	3
all_values[10]	auto[0]	auto[0]	153	1		T2	5		T14	2		T7	3
all_values[10]	auto[0]	auto[1]	54	1		T2	1		T14	2		T15	4
all_values[10]	auto[1]	auto[0]	94	1		T2	2		T7	1		T15	2
all_values[10]	auto[1]	auto[1]	64	1		T14	1		T7	1		T39	2
all_values[11]	auto[0]	auto[0]	144	1		T2	2		T7	1		T15	2
all_values[11]	auto[0]	auto[1]	66	1		T2	3		T14	2		T7	3
all_values[11]	auto[1]	auto[0]	101	1		T2	1		T14	3		T15	3
all_values[11]	auto[1]	auto[1]	54	1		T2	2		T7	1		T15	1
all_values[12]	auto[0]	auto[0]	145	1		T2	2		T14	1		T7	2
all_values[12]	auto[0]	auto[1]	64	1		T2	1		T14	2		T15	1
all_values[12]	auto[1]	auto[0]	76	1		T2	3		T14	2		T7	1
all_values[12]	auto[1]	auto[1]	80	1		T2	2		T7	2		T15	2
all_values[13]	auto[0]	auto[0]	134	1		T2	5		T7	4		T15	1
all_values[13]	auto[0]	auto[1]	76	1		T2	1		T16	1		T36	1
all_values[13]	auto[1]	auto[0]	89	1		T2	1		T14	2		T7	1
all_values[13]	auto[1]	auto[1]	66	1		T2	1		T14	3		T15	4
all_values[14]	auto[0]	auto[0]	149	1		T2	2		T14	1		T7	1
all_values[14]	auto[0]	auto[1]	65	1		T2	4		T7	1		T15	2
all_values[14]	auto[1]	auto[0]	87	1		T14	3		T7	1		T15	3
all_values[14]	auto[1]	auto[1]	64	1		T2	2		T14	1		T7	2
all_values[15]	auto[0]	auto[0]	124	1		T2	4		T14	4		T7	1
all_values[15]	auto[0]	auto[1]	61	1		T2	2		T7	4		T15	2
all_values[15]	auto[1]	auto[0]	98	1		T2	1		T14	1		T16	1
all_values[15]	auto[1]	auto[1]	82	1		T2	1		T15	2		T36	3
all_values[16]	auto[0]	auto[0]	124	1		T14	1		T7	1		T15	1
all_values[16]	auto[0]	auto[1]	69	1		T2	4		T7	2		T15	3
all_values[16]	auto[1]	auto[0]	96	1		T2	1		T14	1		T15	4
all_values[16]	auto[1]	auto[1]	76	1		T2	3		T14	3		T7	2
all_values[17]	auto[0]	auto[0]	158	1		T2	2		T14	3		T15	1
all_values[17]	auto[0]	auto[1]	68	1		T2	1		T14	2		T16	1
all_values[17]	auto[1]	auto[0]	91	1		T2	4		T7	4		T15	4
all_values[17]	auto[1]	auto[1]	48	1		T2	1		T7	1		T15	3