Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
60.95	65.68	59.58	86.57	0.00	69.84	97.77	47.24

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
52.93	52.93	62.14	62.14	50.97	50.97	85.68	85.68	0.00	0.00	63.25	63.25	91.62	91.62	16.83	16.83	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3339970992
57.15	4.22	62.89	0.76	52.13	1.16	89.44	3.76	0.00	0.00	63.33	0.08	91.90	0.28	40.36	23.53	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1280906635
59.60	2.45	65.24	2.35	57.58	5.45	91.78	2.35	0.00	0.00	69.76	6.43	92.46	0.56	40.36	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3602684605
60.60	1.00	65.24	0.00	58.74	1.16	94.60	2.82	0.00	0.00	69.84	0.08	93.58	1.12	42.17	1.81	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1686335504
61.08	0.49	65.24	0.00	58.74	0.00	94.84	0.23	0.00	0.00	69.84	0.00	93.58	0.00	45.34	3.17	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3006469984
61.55	0.47	65.32	0.08	59.13	0.40	94.84	0.00	0.00	0.00	69.84	0.00	96.37	2.79	45.34	0.00	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.867931148
61.75	0.20	65.32	0.00	59.13	0.00	94.84	0.00	0.00	0.00	69.84	0.00	97.77	1.40	45.34	0.00	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2201921839
61.89	0.14	65.32	0.00	59.13	0.00	94.84	0.00	0.00	0.00	69.84	0.00	97.77	0.00	46.33	1.00	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3894640415
61.96	0.07	65.51	0.19	59.46	0.33	94.84	0.00	0.00	0.00	69.84	0.00	97.77	0.00	46.33	0.00	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2338099483
62.03	0.07	65.51	0.00	59.46	0.00	95.31	0.47	0.00	0.00	69.84	0.00	97.77	0.00	46.33	0.00	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.94930928
62.10	0.06	65.51	0.00	59.46	0.00	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	46.79	0.45	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1585646111
62.13	0.03	65.68	0.17	59.51	0.05	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	46.79	0.00	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3706266850
62.16	0.03	65.68	0.00	59.53	0.02	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	46.97	0.18	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.378133059
62.18	0.03	65.68	0.00	59.53	0.00	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	47.15	0.18	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3241051750
62.19	0.01	65.68	0.00	59.53	0.00	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	47.24	0.09	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.258189129
62.20	0.01	65.68	0.00	59.55	0.02	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	47.24	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.822739405
62.20	0.01	65.68	0.00	59.58	0.02	95.31	0.00	0.00	0.00	69.84	0.00	97.77	0.00	47.24	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.617076337

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2048272446
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3190154465
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.746541646
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.903066479
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.505077600
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.413585687
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.525310213
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2984888374
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.727943547
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.725665096
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1608239106
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.99351265
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1102376525
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2645661172
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.975356773
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101724277
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2618706782
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1311721315
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.90694424
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2520913314
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2894829470
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2542504083
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1094056858
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3970361983
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4085495774
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.766900663
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2409859157
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2092861599
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.518621535
/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3068469973
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.612596913
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2666098491
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1412971533
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2686455344
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2758258218
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3704928290
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3845957163
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3285286317
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.237956341
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3925067813
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4026121915
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3049158394
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2498152879
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3327980526
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.70799003
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3950615142
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2995545249
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1888144682
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3583822746
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2772112200
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1261136529
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3707186902
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1487591210
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1895610206
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2473428016
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.154850514
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2077705677
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2543392608
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1081937164
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2640843980
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3647739578
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.89740473
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3910168191
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1046339073
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1859838225
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3619284999
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2566382062
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1357443716
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1733827371
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3378773186
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2470803611
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3080259287
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3522278685
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1328125746
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1403117015
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.845115808
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.359335458
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.257860439
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1966932109
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4038817508
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2479020629
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2290711809
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.1744685470
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1579544123
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.971047803
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4247667858
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.62025073
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.853962075
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2878323456
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3235589292
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3625316876
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3877213551
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.725174372
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3460462799
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1709536215
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3694511759
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4056002574
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3394679351
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3636969214
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.451886284
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1387981978
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1545510533
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2336936967
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3542712731
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.850845263
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.907209138
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1533266567
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.948023167
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3648753140
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.4193654773
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.34886206
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3413944587
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.788687184
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.332041836
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1649025593
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.406334151
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2569380649
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2260763884
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3870442857
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3146643736
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1729075300
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.776738980
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.587804548
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.123306463
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1208553022
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.885041359
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1289627629
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.142026539
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3112221459
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.4171064060
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3529416516
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1812741794
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1968701814
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1678268618
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3717112063
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4115911335
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.533160790
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.959433874
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.541317330
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.525703421
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3707455444
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1970243920
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2802423900
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.738451090
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1717997674
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3037877035
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.106803117
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2636802564
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.506341475
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.884606500
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1744003996
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.824224441
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2768621084
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2078082781
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.297213096
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.704938413
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2064171124
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1952653568

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.257860439	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:02 PM PDT 24	123363904 ps
T2	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2336936967	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	81926288 ps
T3	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.725665096	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:09 PM PDT 24	724305626 ps
T8	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2520913314	Aug 03 04:33:01 PM PDT 24	Aug 03 04:33:02 PM PDT 24	45202474 ps
T14	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1412971533	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	33263630 ps
T4	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.237956341	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:04 PM PDT 24	183932106 ps
T5	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1261136529	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:07 PM PDT 24	514642489 ps
T6	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3339970992	Aug 03 04:34:32 PM PDT 24	Aug 03 04:34:34 PM PDT 24	453984130 ps
T7	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.4193654773	Aug 03 04:33:12 PM PDT 24	Aug 03 04:33:13 PM PDT 24	87281068 ps
T17	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3625316876	Aug 03 04:32:50 PM PDT 24	Aug 03 04:32:52 PM PDT 24	71613264 ps
T9	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3704928290	Aug 03 04:32:57 PM PDT 24	Aug 03 04:33:00 PM PDT 24	633729849 ps
T15	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1280906635	Aug 03 04:33:16 PM PDT 24	Aug 03 04:33:17 PM PDT 24	39097929 ps
T16	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.907209138	Aug 03 04:34:41 PM PDT 24	Aug 03 04:34:42 PM PDT 24	38350408 ps
T32	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.738451090	Aug 03 04:33:15 PM PDT 24	Aug 03 04:33:16 PM PDT 24	142158082 ps
T27	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2077705677	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:12 PM PDT 24	1233792867 ps
T33	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2618706782	Aug 03 04:32:57 PM PDT 24	Aug 03 04:32:58 PM PDT 24	154981760 ps
T18	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.612596913	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:11 PM PDT 24	154956006 ps
T28	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.378133059	Aug 03 04:32:57 PM PDT 24	Aug 03 04:33:01 PM PDT 24	576337984 ps
T35	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.867931148	Aug 03 04:33:01 PM PDT 24	Aug 03 04:33:02 PM PDT 24	201905738 ps
T36	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.1744685470	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:11 PM PDT 24	62886611 ps
T37	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2092861599	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:08 PM PDT 24	85025756 ps
T38	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.853962075	Aug 03 04:33:21 PM PDT 24	Aug 03 04:33:21 PM PDT 24	86281236 ps
T39	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1545510533	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	73167783 ps
T40	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2473428016	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:10 PM PDT 24	87208415 ps
T41	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3006469984	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:55 PM PDT 24	51205654 ps
T42	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.34886206	Aug 03 04:33:20 PM PDT 24	Aug 03 04:33:21 PM PDT 24	85397955 ps
T43	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.359335458	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:56 PM PDT 24	43236012 ps
T71	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3529416516	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:14 PM PDT 24	117590043 ps
T19	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1686335504	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:12 PM PDT 24	158042170 ps
T20	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.975356773	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:07 PM PDT 24	164579501 ps
T44	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2201921839	Aug 03 04:32:47 PM PDT 24	Aug 03 04:32:49 PM PDT 24	81219927 ps
T21	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1733827371	Aug 03 04:33:19 PM PDT 24	Aug 03 04:33:22 PM PDT 24	82652215 ps
T22	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1812741794	Aug 03 04:32:52 PM PDT 24	Aug 03 04:32:54 PM PDT 24	93188018 ps
T45	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.766900663	Aug 03 04:33:15 PM PDT 24	Aug 03 04:33:16 PM PDT 24	53412843 ps
T55	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.297213096	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	60546074 ps
T29	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4115911335	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:06 PM PDT 24	984283338 ps
T73	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2640843980	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:13 PM PDT 24	83096755 ps
T76	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3542712731	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	40106138 ps
T84	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2542504083	Aug 03 04:33:08 PM PDT 24	Aug 03 04:33:09 PM PDT 24	86798572 ps
T72	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3241051750	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	83260874 ps
T70	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3647739578	Aug 03 04:33:03 PM PDT 24	Aug 03 04:33:04 PM PDT 24	87870708 ps
T30	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1970243920	Aug 03 04:32:52 PM PDT 24	Aug 03 04:32:58 PM PDT 24	1083454590 ps
T85	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.884606500	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:54 PM PDT 24	59180539 ps
T31	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1585646111	Aug 03 04:32:58 PM PDT 24	Aug 03 04:33:03 PM PDT 24	730066020 ps
T23	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2566382062	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	121942877 ps
T74	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3894640415	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	78868361 ps
T24	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2260763884	Aug 03 04:32:56 PM PDT 24	Aug 03 04:33:01 PM PDT 24	775261830 ps
T46	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1968701814	Aug 03 04:32:51 PM PDT 24	Aug 03 04:32:52 PM PDT 24	81499480 ps
T25	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.106803117	Aug 03 04:33:15 PM PDT 24	Aug 03 04:33:18 PM PDT 24	105142515 ps
T62	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2636802564	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:12 PM PDT 24	328475485 ps
T65	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.70799003	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:13 PM PDT 24	172577288 ps
T26	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2569380649	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:13 PM PDT 24	153210002 ps
T75	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1533266567	Aug 03 04:33:22 PM PDT 24	Aug 03 04:33:22 PM PDT 24	90210583 ps
T86	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3394679351	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:10 PM PDT 24	376765260 ps
T87	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1208553022	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:14 PM PDT 24	63941838 ps
T88	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2686455344	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:02 PM PDT 24	91616579 ps
T34	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.845115808	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:55 PM PDT 24	74041734 ps
T89	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1895610206	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	53369874 ps
T90	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.903066479	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:57 PM PDT 24	50206706 ps
T91	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.413585687	Aug 03 04:32:48 PM PDT 24	Aug 03 04:32:53 PM PDT 24	485137015 ps
T56	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.617076337	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:04 PM PDT 24	145305517 ps
T92	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3068469973	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:13 PM PDT 24	433040711 ps
T80	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4026121915	Aug 03 04:33:12 PM PDT 24	Aug 03 04:33:14 PM PDT 24	374179933 ps
T93	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1678268618	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	100402215 ps
T94	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.971047803	Aug 03 04:33:08 PM PDT 24	Aug 03 04:33:09 PM PDT 24	40304451 ps
T66	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.506341475	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:58 PM PDT 24	234284910 ps
T95	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1966932109	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:58 PM PDT 24	105084013 ps
T67	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.525703421	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:12 PM PDT 24	139984398 ps
T68	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3583822746	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	210733777 ps
T69	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2802423900	Aug 03 04:33:05 PM PDT 24	Aug 03 04:33:07 PM PDT 24	171087499 ps
T63	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.525310213	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	85279133 ps
T96	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3037877035	Aug 03 04:32:58 PM PDT 24	Aug 03 04:33:00 PM PDT 24	188784343 ps
T57	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3146643736	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:56 PM PDT 24	102423349 ps
T97	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1717997674	Aug 03 04:33:03 PM PDT 24	Aug 03 04:33:04 PM PDT 24	57764902 ps
T98	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.948023167	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:10 PM PDT 24	60478591 ps
T99	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2894829470	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:11 PM PDT 24	119825944 ps
T100	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3413944587	Aug 03 04:32:51 PM PDT 24	Aug 03 04:32:55 PM PDT 24	369505470 ps
T101	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1744003996	Aug 03 04:33:14 PM PDT 24	Aug 03 04:33:14 PM PDT 24	55049917 ps
T102	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.533160790	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:55 PM PDT 24	58217694 ps
T47	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3378773186	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	74332147 ps
T103	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1046339073	Aug 03 04:33:03 PM PDT 24	Aug 03 04:33:04 PM PDT 24	101965290 ps
T58	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3925067813	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:14 PM PDT 24	132068363 ps
T104	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.746541646	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:57 PM PDT 24	78922044 ps
T48	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1709536215	Aug 03 04:32:59 PM PDT 24	Aug 03 04:33:01 PM PDT 24	80813045 ps
T81	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1387981978	Aug 03 04:32:59 PM PDT 24	Aug 03 04:33:02 PM PDT 24	289984776 ps
T59	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1094056858	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:04 PM PDT 24	158511820 ps
T64	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.822739405	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:54 PM PDT 24	58684538 ps
T105	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3648753140	Aug 03 04:33:19 PM PDT 24	Aug 03 04:33:20 PM PDT 24	40949375 ps
T106	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.62025073	Aug 03 04:34:32 PM PDT 24	Aug 03 04:34:33 PM PDT 24	63523350 ps
T107	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101724277	Aug 03 04:32:56 PM PDT 24	Aug 03 04:33:00 PM PDT 24	166030555 ps
T79	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3910168191	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:12 PM PDT 24	931706831 ps
T60	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.154850514	Aug 03 04:33:12 PM PDT 24	Aug 03 04:33:14 PM PDT 24	152745012 ps
T108	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2290711809	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:12 PM PDT 24	37432904 ps
T52	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1102376525	Aug 03 04:32:51 PM PDT 24	Aug 03 04:32:52 PM PDT 24	51671469 ps
T10	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3602684605	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:01 PM PDT 24	111111617 ps
T77	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1952653568	Aug 03 04:33:08 PM PDT 24	Aug 03 04:33:14 PM PDT 24	1226073726 ps
T109	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3717112063	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:12 PM PDT 24	98719699 ps
T49	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.505077600	Aug 03 04:32:49 PM PDT 24	Aug 03 04:32:51 PM PDT 24	110785139 ps
T110	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.541317330	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:11 PM PDT 24	33366771 ps
T111	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1487591210	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:09 PM PDT 24	53231174 ps
T112	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1888144682	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	47337756 ps
T113	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1649025593	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:55 PM PDT 24	66851051 ps
T114	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4247667858	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:13 PM PDT 24	47999555 ps
T115	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2645661172	Aug 03 04:32:47 PM PDT 24	Aug 03 04:32:47 PM PDT 24	116905582 ps
T61	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4038817508	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:55 PM PDT 24	73821633 ps
T116	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3235589292	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:12 PM PDT 24	53454043 ps
T50	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3190154465	Aug 03 04:32:50 PM PDT 24	Aug 03 04:32:57 PM PDT 24	1085778709 ps
T82	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3970361983	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:58 PM PDT 24	548311723 ps
T117	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.406334151	Aug 03 04:32:48 PM PDT 24	Aug 03 04:32:49 PM PDT 24	51315057 ps
T118	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.587804548	Aug 03 04:33:15 PM PDT 24	Aug 03 04:33:16 PM PDT 24	47823309 ps
T11	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.94930928	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:57 PM PDT 24	102524893 ps
T119	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.850845263	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	114108694 ps
T120	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.89740473	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:04 PM PDT 24	105940108 ps
T78	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.258189129	Aug 03 04:32:48 PM PDT 24	Aug 03 04:32:54 PM PDT 24	1186963382 ps
T121	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.99351265	Aug 03 04:32:55 PM PDT 24	Aug 03 04:32:58 PM PDT 24	88079833 ps
T122	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3845957163	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	89091924 ps
T123	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.4171064060	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:10 PM PDT 24	47345048 ps
T124	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3707455444	Aug 03 04:32:51 PM PDT 24	Aug 03 04:32:55 PM PDT 24	107491460 ps
T125	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2338099483	Aug 03 04:33:03 PM PDT 24	Aug 03 04:33:07 PM PDT 24	300711469 ps
T126	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.704938413	Aug 03 04:32:55 PM PDT 24	Aug 03 04:32:56 PM PDT 24	36621959 ps
T127	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2543392608	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:08 PM PDT 24	121793921 ps
T128	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3285286317	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	80477086 ps
T51	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.959433874	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:55 PM PDT 24	83815737 ps
T129	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3706266850	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:08 PM PDT 24	265763554 ps
T130	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1081937164	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	69625239 ps
T131	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2878323456	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:12 PM PDT 24	43009242 ps
T132	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1289627629	Aug 03 04:33:14 PM PDT 24	Aug 03 04:33:15 PM PDT 24	43976293 ps
T133	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3619284999	Aug 03 04:33:11 PM PDT 24	Aug 03 04:33:12 PM PDT 24	114360274 ps
T134	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1729075300	Aug 03 04:33:08 PM PDT 24	Aug 03 04:33:14 PM PDT 24	2225218157 ps
T53	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2048272446	Aug 03 04:32:52 PM PDT 24	Aug 03 04:32:54 PM PDT 24	80500049 ps
T83	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1311721315	Aug 03 04:32:48 PM PDT 24	Aug 03 04:32:51 PM PDT 24	815760717 ps
T135	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2498152879	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	98202087 ps
T136	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2984888374	Aug 03 04:32:50 PM PDT 24	Aug 03 04:32:52 PM PDT 24	157973002 ps
T137	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.776738980	Aug 03 04:33:15 PM PDT 24	Aug 03 04:33:16 PM PDT 24	70625482 ps
T138	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3522278685	Aug 03 04:33:01 PM PDT 24	Aug 03 04:33:03 PM PDT 24	65058574 ps
T139	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.332041836	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:09 PM PDT 24	170548943 ps
T140	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2768621084	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:06 PM PDT 24	218135694 ps
T141	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3080259287	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:11 PM PDT 24	111102291 ps
T142	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2995545249	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:06 PM PDT 24	132453759 ps
T143	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.451886284	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:10 PM PDT 24	163709076 ps
T144	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2078082781	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:56 PM PDT 24	72127635 ps
T12	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1403117015	Aug 03 04:32:49 PM PDT 24	Aug 03 04:32:50 PM PDT 24	70328153 ps
T145	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2666098491	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:08 PM PDT 24	74427893 ps
T146	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3636969214	Aug 03 04:32:53 PM PDT 24	Aug 03 04:32:55 PM PDT 24	170822367 ps
T54	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1859838225	Aug 03 04:33:06 PM PDT 24	Aug 03 04:33:07 PM PDT 24	87996149 ps
T147	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.90694424	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:12 PM PDT 24	71009402 ps
T148	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1357443716	Aug 03 04:33:14 PM PDT 24	Aug 03 04:33:18 PM PDT 24	545606707 ps
T149	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.788687184	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:10 PM PDT 24	1349516957 ps
T150	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2772112200	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:05 PM PDT 24	231365241 ps
T151	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.518621535	Aug 03 04:33:05 PM PDT 24	Aug 03 04:33:08 PM PDT 24	95971232 ps
T152	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3694511759	Aug 03 04:32:55 PM PDT 24	Aug 03 04:32:56 PM PDT 24	53222909 ps
T153	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1579544123	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:14 PM PDT 24	43129043 ps
T154	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4056002574	Aug 03 04:32:56 PM PDT 24	Aug 03 04:32:58 PM PDT 24	166535050 ps
T155	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.123306463	Aug 03 04:33:16 PM PDT 24	Aug 03 04:33:17 PM PDT 24	85426049 ps
T156	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3112221459	Aug 03 04:33:13 PM PDT 24	Aug 03 04:33:14 PM PDT 24	59921754 ps
T13	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1608239106	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:01 PM PDT 24	63517390 ps
T157	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2064171124	Aug 03 04:33:07 PM PDT 24	Aug 03 04:33:08 PM PDT 24	97806099 ps
T158	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.725174372	Aug 03 04:32:55 PM PDT 24	Aug 03 04:32:56 PM PDT 24	70517592 ps
T159	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4085495774	Aug 03 04:33:00 PM PDT 24	Aug 03 04:33:01 PM PDT 24	64513845 ps
T160	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.885041359	Aug 03 04:33:21 PM PDT 24	Aug 03 04:33:22 PM PDT 24	60825150 ps
T161	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3707186902	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:06 PM PDT 24	89081485 ps
T162	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3460462799	Aug 03 04:33:01 PM PDT 24	Aug 03 04:33:03 PM PDT 24	156631228 ps
T163	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3950615142	Aug 03 04:33:19 PM PDT 24	Aug 03 04:33:21 PM PDT 24	143829901 ps
T164	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2479020629	Aug 03 04:32:49 PM PDT 24	Aug 03 04:32:54 PM PDT 24	777694147 ps
T165	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2470803611	Aug 03 04:33:20 PM PDT 24	Aug 03 04:33:20 PM PDT 24	52201880 ps
T166	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3877213551	Aug 03 04:32:54 PM PDT 24	Aug 03 04:32:59 PM PDT 24	931101222 ps
T167	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.824224441	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	134677126 ps
T168	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2409859157	Aug 03 04:33:02 PM PDT 24	Aug 03 04:33:03 PM PDT 24	39447997 ps
T169	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.142026539	Aug 03 04:33:12 PM PDT 24	Aug 03 04:33:13 PM PDT 24	44017225 ps
T170	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2758258218	Aug 03 04:33:04 PM PDT 24	Aug 03 04:33:05 PM PDT 24	62242530 ps
T171	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3049158394	Aug 03 04:33:10 PM PDT 24	Aug 03 04:33:11 PM PDT 24	113065481 ps
T172	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1328125746	Aug 03 04:32:49 PM PDT 24	Aug 03 04:32:54 PM PDT 24	325790235 ps
T173	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.727943547	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:13 PM PDT 24	302650690 ps
T174	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3327980526	Aug 03 04:33:09 PM PDT 24	Aug 03 04:33:10 PM PDT 24	57082496 ps
T175	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3870442857	Aug 03 04:33:03 PM PDT 24	Aug 03 04:33:05 PM PDT 24	144934864 ps

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3339970992
Short name	T6
Test name
Test status
Simulation time	453984130 ps
CPU time	2.35 seconds
Started	Aug 03 04:34:32 PM PDT 24
Finished	Aug 03 04:34:34 PM PDT 24
Peak memory	206884 kb
Host	smart-7e90c823-6e5d-481b-8b8a-8b7d8495b22e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3339970992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3339970992
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.1280906635
Short name	T15
Test name
Test status
Simulation time	39097929 ps
CPU time	0.76 seconds
Started	Aug 03 04:33:16 PM PDT 24
Finished	Aug 03 04:33:17 PM PDT 24
Peak memory	206760 kb
Host	smart-82a61415-59f5-449f-a1e2-6ebe048a0440
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1280906635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1280906635
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3602684605
Short name	T10
Test name
Test status
Simulation time	111111617 ps
CPU time	0.98 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	206812 kb
Host	smart-db863b7a-b419-4ba7-af62-8ace2e51afe2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3602684605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3602684605
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1686335504
Short name	T19
Test name
Test status
Simulation time	158042170 ps
CPU time	1.99 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207044 kb
Host	smart-a145f25e-db93-4a12-9a93-14cfb23e858f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1686335504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1686335504
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.3006469984
Short name	T41
Test name
Test status
Simulation time	51205654 ps
CPU time	0.74 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	206868 kb
Host	smart-91b01983-8ccb-488a-941a-5ecfe56efc33
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3006469984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3006469984
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.867931148
Short name	T35
Test name
Test status
Simulation time	201905738 ps
CPU time	1.47 seconds
Started	Aug 03 04:33:01 PM PDT 24
Finished	Aug 03 04:33:02 PM PDT 24
Peak memory	207120 kb
Host	smart-295499ec-6d17-4f3a-8dd0-58e5401ed20d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=867931148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.867931148
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2201921839
Short name	T44
Test name
Test status
Simulation time	81219927 ps
CPU time	2.01 seconds
Started	Aug 03 04:32:47 PM PDT 24
Finished	Aug 03 04:32:49 PM PDT 24
Peak memory	207120 kb
Host	smart-a2b98e2d-84bc-4045-af73-e4061c2cbdc5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2201921839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2201921839
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.3894640415
Short name	T74
Test name
Test status
Simulation time	78868361 ps
CPU time	0.78 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206832 kb
Host	smart-3574eae8-ff7e-4327-adb0-2d967a19483a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3894640415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3894640415
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2338099483
Short name	T125
Test name
Test status
Simulation time	300711469 ps
CPU time	3.61 seconds
Started	Aug 03 04:33:03 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	223404 kb
Host	smart-977630f4-9963-48c4-80ab-731d01ca0437
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2338099483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2338099483
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.94930928
Short name	T11
Test name
Test status
Simulation time	102524893 ps
CPU time	0.91 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:57 PM PDT 24
Peak memory	206888 kb
Host	smart-06106140-196b-42a7-a320-f53254e0d6c2
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=94930928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.94930928
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1585646111
Short name	T31
Test name
Test status
Simulation time	730066020 ps
CPU time	4.6 seconds
Started	Aug 03 04:32:58 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	207120 kb
Host	smart-ab6982e3-5517-457e-a997-954e841b57ba
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1585646111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1585646111
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.3706266850
Short name	T129
Test name
Test status
Simulation time	265763554 ps
CPU time	2.94 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	222816 kb
Host	smart-13975a8f-dcda-49cf-a6bd-dac48f760f8a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3706266850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.3706266850
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.378133059
Short name	T28
Test name
Test status
Simulation time	576337984 ps
CPU time	4.47 seconds
Started	Aug 03 04:32:57 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	207172 kb
Host	smart-08f66589-760a-4fae-af19-5d88496dca82
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=378133059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.378133059
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3241051750
Short name	T72
Test name
Test status
Simulation time	83260874 ps
CPU time	0.74 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206784 kb
Host	smart-635ba901-b3cb-401a-ab91-8c4ccf3b9238
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3241051750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3241051750
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.258189129
Short name	T78
Test name
Test status
Simulation time	1186963382 ps
CPU time	5.44 seconds
Started	Aug 03 04:32:48 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	207184 kb
Host	smart-b946f8df-4b6e-4c99-8b97-2b6fe97e49ca
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=258189129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.258189129
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.822739405
Short name	T64
Test name
Test status
Simulation time	58684538 ps
CPU time	1.21 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	215376 kb
Host	smart-f0597da6-7fbd-4e0f-a4b6-243b1e4da9c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822739405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev _csr_mem_rw_with_rand_reset.822739405
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.617076337
Short name	T56
Test name
Test status
Simulation time	145305517 ps
CPU time	1.94 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	207156 kb
Host	smart-a949f055-9301-4fab-919e-5ca8d464e785
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=617076337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.617076337
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.2048272446
Short name	T53
Test name
Test status
Simulation time	80500049 ps
CPU time	1.9 seconds
Started	Aug 03 04:32:52 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	206976 kb
Host	smart-c0197ba7-731e-40d7-af90-e7ab143de75f
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2048272446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.2048272446
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3190154465
Short name	T50
Test name
Test status
Simulation time	1085778709 ps
CPU time	7.61 seconds
Started	Aug 03 04:32:50 PM PDT 24
Finished	Aug 03 04:32:57 PM PDT 24
Peak memory	207060 kb
Host	smart-6005a6a2-e414-4559-a6bf-c08b1631627d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3190154465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3190154465
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.746541646
Short name	T104
Test name
Test status
Simulation time	78922044 ps
CPU time	0.87 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:57 PM PDT 24
Peak memory	206792 kb
Host	smart-d4b9cb33-0a78-42df-a715-ea02deb6885e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=746541646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.746541646
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.903066479
Short name	T90
Test name
Test status
Simulation time	50206706 ps
CPU time	0.75 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:57 PM PDT 24
Peak memory	206728 kb
Host	smart-6dbbbc0b-db0f-433f-a32f-31a9fba28bdf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=903066479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.903066479
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.505077600
Short name	T49
Test name
Test status
Simulation time	110785139 ps
CPU time	1.47 seconds
Started	Aug 03 04:32:49 PM PDT 24
Finished	Aug 03 04:32:51 PM PDT 24
Peak memory	215036 kb
Host	smart-287ba09a-6b1c-46f0-bdfa-5878c089bbf0
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=505077600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.505077600
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.413585687
Short name	T91
Test name
Test status
Simulation time	485137015 ps
CPU time	4.43 seconds
Started	Aug 03 04:32:48 PM PDT 24
Finished	Aug 03 04:32:53 PM PDT 24
Peak memory	207020 kb
Host	smart-00ab5832-8338-47bd-a75a-e6cefa1aa551
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=413585687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.413585687
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.525310213
Short name	T63
Test name
Test status
Simulation time	85279133 ps
CPU time	1.1 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	207044 kb
Host	smart-cafac7f7-5973-4a9f-807a-5291488d07ac
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=525310213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.525310213
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2984888374
Short name	T136
Test name
Test status
Simulation time	157973002 ps
CPU time	2.83 seconds
Started	Aug 03 04:32:50 PM PDT 24
Finished	Aug 03 04:32:52 PM PDT 24
Peak memory	215328 kb
Host	smart-6f8b4656-7bd0-46f7-8c2a-958210b6496d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2984888374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2984888374
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.727943547
Short name	T173
Test name
Test status
Simulation time	302650690 ps
CPU time	3.76 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	207028 kb
Host	smart-016d21bb-b69e-4861-a1d9-f2e1508ca75b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=727943547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.727943547
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.725665096
Short name	T3
Test name
Test status
Simulation time	724305626 ps
CPU time	4.57 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:09 PM PDT 24
Peak memory	207108 kb
Host	smart-380d19bd-3946-47e3-a9de-8f6d1f4ea7b4
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=725665096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.725665096
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1608239106
Short name	T13
Test name
Test status
Simulation time	63517390 ps
CPU time	0.79 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	206808 kb
Host	smart-a46eb228-61a3-4480-998b-a9cb16035c0f
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1608239106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.1608239106
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.99351265
Short name	T121
Test name
Test status
Simulation time	88079833 ps
CPU time	2.38 seconds
Started	Aug 03 04:32:55 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	215288 kb
Host	smart-a40c1680-7f29-480d-84ae-6e62a160893d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99351265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_ csr_mem_rw_with_rand_reset.99351265
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1102376525
Short name	T52
Test name
Test status
Simulation time	51671469 ps
CPU time	0.91 seconds
Started	Aug 03 04:32:51 PM PDT 24
Finished	Aug 03 04:32:52 PM PDT 24
Peak memory	206856 kb
Host	smart-db96a50b-ba52-430d-b560-ea540fb29fda
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1102376525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1102376525
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.2645661172
Short name	T115
Test name
Test status
Simulation time	116905582 ps
CPU time	0.79 seconds
Started	Aug 03 04:32:47 PM PDT 24
Finished	Aug 03 04:32:47 PM PDT 24
Peak memory	206844 kb
Host	smart-ddf573e4-b7c4-412f-8af9-dfb8b6f77995
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2645661172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2645661172
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.975356773
Short name	T20
Test name
Test status
Simulation time	164579501 ps
CPU time	2.29 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	215220 kb
Host	smart-89de1a2c-db22-4365-9ad7-37a02d2ae7a6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=975356773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.975356773
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3101724277
Short name	T107
Test name
Test status
Simulation time	166030555 ps
CPU time	4.06 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:33:00 PM PDT 24
Peak memory	206980 kb
Host	smart-56417e0c-9511-443d-bb49-0e00541b1edc
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3101724277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3101724277
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2618706782
Short name	T33
Test name
Test status
Simulation time	154981760 ps
CPU time	1.34 seconds
Started	Aug 03 04:32:57 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	207032 kb
Host	smart-912ec1f0-882d-4dbe-8f3f-d76494296cde
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2618706782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2618706782
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1311721315
Short name	T83
Test name
Test status
Simulation time	815760717 ps
CPU time	2.94 seconds
Started	Aug 03 04:32:48 PM PDT 24
Finished	Aug 03 04:32:51 PM PDT 24
Peak memory	207148 kb
Host	smart-8b6041b4-a90a-44b0-ad33-48aa3e0fb4cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1311721315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1311721315
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.90694424
Short name	T147
Test name
Test status
Simulation time	71009402 ps
CPU time	1.51 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	215532 kb
Host	smart-33ba259d-401d-4fc1-a38f-fa92ce90c8ff
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90694424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev _csr_mem_rw_with_rand_reset.90694424
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2520913314
Short name	T8
Test name
Test status
Simulation time	45202474 ps
CPU time	0.8 seconds
Started	Aug 03 04:33:01 PM PDT 24
Finished	Aug 03 04:33:02 PM PDT 24
Peak memory	206904 kb
Host	smart-3553c50e-5733-4076-bae0-4859f2e15ebd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2520913314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2520913314
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.2894829470
Short name	T99
Test name
Test status
Simulation time	119825944 ps
CPU time	0.81 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	206704 kb
Host	smart-0dcfcea6-1783-4626-a01c-ea806e2d0755
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2894829470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2894829470
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2542504083
Short name	T84
Test name
Test status
Simulation time	86798572 ps
CPU time	1.08 seconds
Started	Aug 03 04:33:08 PM PDT 24
Finished	Aug 03 04:33:09 PM PDT 24
Peak memory	207080 kb
Host	smart-009e9c15-61fa-45f7-98ae-981262fa9c8d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2542504083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2542504083
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1094056858
Short name	T59
Test name
Test status
Simulation time	158511820 ps
CPU time	2.12 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	207028 kb
Host	smart-d190d902-30a9-4065-bef7-3446042ea867
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1094056858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1094056858
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3970361983
Short name	T82
Test name
Test status
Simulation time	548311723 ps
CPU time	4.58 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	207108 kb
Host	smart-6190d216-b93a-4c0c-bcb5-e5dd5090adaa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3970361983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3970361983
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.4085495774
Short name	T159
Test name
Test status
Simulation time	64513845 ps
CPU time	1.39 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	215360 kb
Host	smart-fcdc4796-ed04-473c-9465-7db1f90ed667
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085495774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.4085495774
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.766900663
Short name	T45
Test name
Test status
Simulation time	53412843 ps
CPU time	0.83 seconds
Started	Aug 03 04:33:15 PM PDT 24
Finished	Aug 03 04:33:16 PM PDT 24
Peak memory	206840 kb
Host	smart-17707a74-936a-47f6-b2cb-4dd78546394d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=766900663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.766900663
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.2409859157
Short name	T168
Test name
Test status
Simulation time	39447997 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206752 kb
Host	smart-d4fa100f-ca71-4a50-a8ca-d8e7e06c6764
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2409859157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2409859157
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2092861599
Short name	T37
Test name
Test status
Simulation time	85025756 ps
CPU time	1.07 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	206824 kb
Host	smart-e8560e70-7a20-40ff-8f88-09e1f5a8459b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2092861599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2092861599
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.518621535
Short name	T151
Test name
Test status
Simulation time	95971232 ps
CPU time	2.75 seconds
Started	Aug 03 04:33:05 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	223072 kb
Host	smart-0e744190-b2d1-4b62-8ed0-1d8ab23e266b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=518621535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.518621535
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3068469973
Short name	T92
Test name
Test status
Simulation time	433040711 ps
CPU time	2.72 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	207120 kb
Host	smart-862b9acc-529c-493e-bb8b-57b07b399465
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3068469973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3068469973
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.612596913
Short name	T18
Test name
Test status
Simulation time	154956006 ps
CPU time	2.02 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	215380 kb
Host	smart-1db9993c-5269-4bb2-9996-cb0f8b40df6f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612596913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde v_csr_mem_rw_with_rand_reset.612596913
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2666098491
Short name	T145
Test name
Test status
Simulation time	74427893 ps
CPU time	1.01 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	206848 kb
Host	smart-b0e13016-610f-471e-9458-34b3f783449e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2666098491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2666098491
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1412971533
Short name	T14
Test name
Test status
Simulation time	33263630 ps
CPU time	0.68 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	206744 kb
Host	smart-54335204-db7d-4e3b-b72a-d02677e78b55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1412971533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1412971533
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2686455344
Short name	T88
Test name
Test status
Simulation time	91616579 ps
CPU time	1.04 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:02 PM PDT 24
Peak memory	206864 kb
Host	smart-6e1a785c-adc6-4bca-b84a-008d49b5dd71
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2686455344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2686455344
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2758258218
Short name	T170
Test name
Test status
Simulation time	62242530 ps
CPU time	1.35 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	207116 kb
Host	smart-08739f13-f9bd-4420-8878-a701f9675ad0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2758258218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2758258218
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3704928290
Short name	T9
Test name
Test status
Simulation time	633729849 ps
CPU time	2.9 seconds
Started	Aug 03 04:32:57 PM PDT 24
Finished	Aug 03 04:33:00 PM PDT 24
Peak memory	207140 kb
Host	smart-ffd0f6ef-aebe-449f-8104-55d98fb34789
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3704928290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3704928290
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.3845957163
Short name	T122
Test name
Test status
Simulation time	89091924 ps
CPU time	1.23 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	215280 kb
Host	smart-f8563bd6-f0db-4f41-893b-a98571002c81
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845957163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.3845957163
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3285286317
Short name	T128
Test name
Test status
Simulation time	80477086 ps
CPU time	1 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206836 kb
Host	smart-bf5b8cd5-15f5-4b65-9c72-973620093c2c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3285286317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3285286317
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.237956341
Short name	T4
Test name
Test status
Simulation time	183932106 ps
CPU time	1.45 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	206996 kb
Host	smart-672301ab-4222-4b85-9b5e-39c907f8e43b
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=237956341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.237956341
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3925067813
Short name	T58
Test name
Test status
Simulation time	132068363 ps
CPU time	3.78 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	223460 kb
Host	smart-981ee975-8205-4d7d-ae2e-7e4b0fb909b7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3925067813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3925067813
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4026121915
Short name	T80
Test name
Test status
Simulation time	374179933 ps
CPU time	2.65 seconds
Started	Aug 03 04:33:12 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	207080 kb
Host	smart-27bfd113-eda1-474e-bebd-cecf01bc3e99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4026121915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4026121915
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3049158394
Short name	T171
Test name
Test status
Simulation time	113065481 ps
CPU time	1.27 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	223536 kb
Host	smart-cff16c25-cb8c-4813-8561-849e4d0d3d00
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049158394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.3049158394
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2498152879
Short name	T135
Test name
Test status
Simulation time	98202087 ps
CPU time	1.07 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206932 kb
Host	smart-da0687bd-3e7a-4308-95d0-a8763600a4eb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2498152879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2498152879
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3327980526
Short name	T174
Test name
Test status
Simulation time	57082496 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	206752 kb
Host	smart-44b8f918-935e-40cb-8b51-076e01e56d10
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3327980526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3327980526
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.70799003
Short name	T65
Test name
Test status
Simulation time	172577288 ps
CPU time	1.48 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	207144 kb
Host	smart-3f1db1b1-0b44-4796-95b7-16b7a60f80e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=70799003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.70799003
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3950615142
Short name	T163
Test name
Test status
Simulation time	143829901 ps
CPU time	1.65 seconds
Started	Aug 03 04:33:19 PM PDT 24
Finished	Aug 03 04:33:21 PM PDT 24
Peak memory	223412 kb
Host	smart-2fbeedd0-decc-42bb-bbfd-bb283adbc65d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950615142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.3950615142
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2995545249
Short name	T142
Test name
Test status
Simulation time	132453759 ps
CPU time	1.07 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:06 PM PDT 24
Peak memory	206924 kb
Host	smart-c26f0a32-fedd-4dca-b9e5-9c19912448d2
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2995545249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2995545249
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.1888144682
Short name	T112
Test name
Test status
Simulation time	47337756 ps
CPU time	0.72 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206652 kb
Host	smart-4b1ecffc-59f7-4603-a757-52b8a2b37b87
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1888144682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.1888144682
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3583822746
Short name	T68
Test name
Test status
Simulation time	210733777 ps
CPU time	1.24 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	207116 kb
Host	smart-4830a034-8305-4c4d-a610-c1ae91d1f2ab
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3583822746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3583822746
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.2772112200
Short name	T150
Test name
Test status
Simulation time	231365241 ps
CPU time	2.21 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	223176 kb
Host	smart-a78e400a-5d8e-494c-91f5-b881069373ad
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2772112200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.2772112200
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1261136529
Short name	T5
Test name
Test status
Simulation time	514642489 ps
CPU time	2.98 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	207040 kb
Host	smart-49f989f3-78b4-4ee7-838d-81cb16cd4a04
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1261136529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1261136529
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3707186902
Short name	T161
Test name
Test status
Simulation time	89081485 ps
CPU time	1.63 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:06 PM PDT 24
Peak memory	215228 kb
Host	smart-34c8b4ac-5bc4-4602-8d73-4626b26ece91
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707186902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.3707186902
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1487591210
Short name	T111
Test name
Test status
Simulation time	53231174 ps
CPU time	0.77 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:09 PM PDT 24
Peak memory	206732 kb
Host	smart-26fe45fe-bd36-4c70-9603-b5a97853acfe
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1487591210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1487591210
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1895610206
Short name	T89
Test name
Test status
Simulation time	53369874 ps
CPU time	0.75 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	206728 kb
Host	smart-7b3b87a2-9c72-4e37-a675-83df68465851
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1895610206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1895610206
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2473428016
Short name	T40
Test name
Test status
Simulation time	87208415 ps
CPU time	1.1 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	207064 kb
Host	smart-47f97849-43a2-49e5-afb8-5e5dcfee38fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2473428016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2473428016
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.154850514
Short name	T60
Test name
Test status
Simulation time	152745012 ps
CPU time	2.08 seconds
Started	Aug 03 04:33:12 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	207104 kb
Host	smart-7172d705-305f-4c28-816d-a37f319067ff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=154850514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.154850514
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.2077705677
Short name	T27
Test name
Test status
Simulation time	1233792867 ps
CPU time	5.24 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207080 kb
Host	smart-865659b1-3ace-4dc7-b5d5-3cd62d6c7dcc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2077705677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.2077705677
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2543392608
Short name	T127
Test name
Test status
Simulation time	121793921 ps
CPU time	2.06 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	215344 kb
Host	smart-a3dbe34b-2691-4ba0-9bf9-962284887137
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543392608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.2543392608
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.1081937164
Short name	T130
Test name
Test status
Simulation time	69625239 ps
CPU time	0.83 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206780 kb
Host	smart-64c7b00a-836d-4703-9ec3-a76156f41d70
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1081937164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.1081937164
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.2640843980
Short name	T73
Test name
Test status
Simulation time	83096755 ps
CPU time	0.75 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	206748 kb
Host	smart-b17a1655-f84f-4e67-90d8-3e106880c798
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2640843980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2640843980
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3647739578
Short name	T70
Test name
Test status
Simulation time	87870708 ps
CPU time	1.12 seconds
Started	Aug 03 04:33:03 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	206896 kb
Host	smart-53bc81c8-c60e-4a28-bc43-fe864fdb50e3
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3647739578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3647739578
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.89740473
Short name	T120
Test name
Test status
Simulation time	105940108 ps
CPU time	2.34 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	207136 kb
Host	smart-c93eb329-f72c-449f-8fc7-efd2fbfc2ba0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=89740473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.89740473
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3910168191
Short name	T79
Test name
Test status
Simulation time	931706831 ps
CPU time	5 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207000 kb
Host	smart-4e77498f-29d1-414b-85ac-35b44d3a9fd7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3910168191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3910168191
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1046339073
Short name	T103
Test name
Test status
Simulation time	101965290 ps
CPU time	1.21 seconds
Started	Aug 03 04:33:03 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	223468 kb
Host	smart-3688eb43-81ff-4fee-87fe-ea3fdb57bc71
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046339073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1046339073
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1859838225
Short name	T54
Test name
Test status
Simulation time	87996149 ps
CPU time	0.91 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	206980 kb
Host	smart-74189a70-588c-41aa-aaec-95a5913bf029
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1859838225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1859838225
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3619284999
Short name	T133
Test name
Test status
Simulation time	114360274 ps
CPU time	1.11 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207044 kb
Host	smart-9047db6d-eccc-4867-960e-13bdb3c7939c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3619284999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3619284999
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2566382062
Short name	T23
Test name
Test status
Simulation time	121942877 ps
CPU time	1.7 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	207048 kb
Host	smart-053599e9-2da2-4506-b91c-69312ed8fe76
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2566382062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2566382062
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1357443716
Short name	T148
Test name
Test status
Simulation time	545606707 ps
CPU time	3.97 seconds
Started	Aug 03 04:33:14 PM PDT 24
Finished	Aug 03 04:33:18 PM PDT 24
Peak memory	207144 kb
Host	smart-b0570b57-9e0f-492e-9216-6ee68c005c98
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1357443716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1357443716
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1733827371
Short name	T21
Test name
Test status
Simulation time	82652215 ps
CPU time	2.09 seconds
Started	Aug 03 04:33:19 PM PDT 24
Finished	Aug 03 04:33:22 PM PDT 24
Peak memory	215416 kb
Host	smart-1874de1d-446c-4942-92e7-12c74c079671
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733827371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.1733827371
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3378773186
Short name	T47
Test name
Test status
Simulation time	74332147 ps
CPU time	0.96 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206828 kb
Host	smart-2aeb8da3-975a-437b-a4f7-1b58492ce3a7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3378773186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3378773186
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2470803611
Short name	T165
Test name
Test status
Simulation time	52201880 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:20 PM PDT 24
Finished	Aug 03 04:33:20 PM PDT 24
Peak memory	206740 kb
Host	smart-56dad946-997b-4f75-bc6a-d76bd161932e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2470803611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2470803611
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3080259287
Short name	T141
Test name
Test status
Simulation time	111102291 ps
CPU time	1.11 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	207196 kb
Host	smart-d0c1c78d-59e6-4f7a-920b-d5a8012e138f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3080259287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3080259287
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3522278685
Short name	T138
Test name
Test status
Simulation time	65058574 ps
CPU time	1.36 seconds
Started	Aug 03 04:33:01 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	207176 kb
Host	smart-fe6a87c0-55a4-407d-9c24-0da7e07988e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3522278685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3522278685
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1328125746
Short name	T172
Test name
Test status
Simulation time	325790235 ps
CPU time	4.39 seconds
Started	Aug 03 04:32:49 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	207052 kb
Host	smart-005d3c62-99f1-47d1-b69e-8f49304985fe
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1328125746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1328125746
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1403117015
Short name	T12
Test name
Test status
Simulation time	70328153 ps
CPU time	0.83 seconds
Started	Aug 03 04:32:49 PM PDT 24
Finished	Aug 03 04:32:50 PM PDT 24
Peak memory	206552 kb
Host	smart-46c55716-aaff-493f-b973-83e524d22354
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1403117015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.1403117015
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.845115808
Short name	T34
Test name
Test status
Simulation time	74041734 ps
CPU time	1.76 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	215196 kb
Host	smart-298daee2-3905-44c1-af86-234cc3dc92a4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845115808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev _csr_mem_rw_with_rand_reset.845115808
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.359335458
Short name	T43
Test name
Test status
Simulation time	43236012 ps
CPU time	0.79 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	206888 kb
Host	smart-5f06b61e-ae94-4d0a-9520-a6e923f7bea0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=359335458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.359335458
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.257860439
Short name	T1
Test name
Test status
Simulation time	123363904 ps
CPU time	1.42 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:02 PM PDT 24
Peak memory	215276 kb
Host	smart-04c15e3a-b7c8-48ed-ab02-cd2cd7f008f7
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=257860439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.257860439
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1966932109
Short name	T95
Test name
Test status
Simulation time	105084013 ps
CPU time	2.24 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	206980 kb
Host	smart-f49db262-1a10-4dca-b038-9e4ff305678a
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1966932109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1966932109
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4038817508
Short name	T61
Test name
Test status
Simulation time	73821633 ps
CPU time	1.71 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	207176 kb
Host	smart-69f51377-3b4f-467c-8a32-eaed667ed587
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4038817508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4038817508
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2479020629
Short name	T164
Test name
Test status
Simulation time	777694147 ps
CPU time	5.14 seconds
Started	Aug 03 04:32:49 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	207004 kb
Host	smart-a7b62193-1097-4fc0-bb01-59a74a781861
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2479020629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2479020629
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.2290711809
Short name	T108
Test name
Test status
Simulation time	37432904 ps
CPU time	0.72 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	206652 kb
Host	smart-708cf750-ac4a-4069-b610-1d87d673c93e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2290711809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2290711809
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.1744685470
Short name	T36
Test name
Test status
Simulation time	62886611 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	206660 kb
Host	smart-c04b6f0e-d433-4105-a491-1953c5406f94
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1744685470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1744685470
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.1579544123
Short name	T153
Test name
Test status
Simulation time	43129043 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206740 kb
Host	smart-ce6af0a9-bd98-4e64-9d73-5a3012580cd1
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1579544123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1579544123
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.971047803
Short name	T94
Test name
Test status
Simulation time	40304451 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:08 PM PDT 24
Finished	Aug 03 04:33:09 PM PDT 24
Peak memory	206772 kb
Host	smart-ebc306b6-a8b9-4cdd-836b-557104a580d9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=971047803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.971047803
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.4247667858
Short name	T114
Test name
Test status
Simulation time	47999555 ps
CPU time	0.74 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	206716 kb
Host	smart-aa088000-f759-4751-b1ac-fcf25291da4c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4247667858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4247667858
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.62025073
Short name	T106
Test name
Test status
Simulation time	63523350 ps
CPU time	0.72 seconds
Started	Aug 03 04:34:32 PM PDT 24
Finished	Aug 03 04:34:33 PM PDT 24
Peak memory	206560 kb
Host	smart-85da676a-1c33-4fa3-99a0-95d625d70906
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=62025073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.62025073
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.853962075
Short name	T38
Test name
Test status
Simulation time	86281236 ps
CPU time	0.78 seconds
Started	Aug 03 04:33:21 PM PDT 24
Finished	Aug 03 04:33:21 PM PDT 24
Peak memory	206752 kb
Host	smart-8e164e70-b688-489e-8cd1-817a84e3c27e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=853962075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.853962075
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.2878323456
Short name	T131
Test name
Test status
Simulation time	43009242 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	206768 kb
Host	smart-93b1a10c-3693-466b-8180-c2e564f5ce55
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2878323456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.2878323456
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3235589292
Short name	T116
Test name
Test status
Simulation time	53454043 ps
CPU time	0.72 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	206648 kb
Host	smart-c43624f3-e5e4-4c65-88d8-0badbfd8d341
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3235589292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3235589292
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3625316876
Short name	T17
Test name
Test status
Simulation time	71613264 ps
CPU time	1.92 seconds
Started	Aug 03 04:32:50 PM PDT 24
Finished	Aug 03 04:32:52 PM PDT 24
Peak memory	207268 kb
Host	smart-363b6d3f-19c4-48b0-9994-0205eafb324a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3625316876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3625316876
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3877213551
Short name	T166
Test name
Test status
Simulation time	931101222 ps
CPU time	4.55 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:59 PM PDT 24
Peak memory	207080 kb
Host	smart-d6f8c529-b458-4500-a1b1-1fe873310489
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3877213551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3877213551
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.725174372
Short name	T158
Test name
Test status
Simulation time	70517592 ps
CPU time	0.9 seconds
Started	Aug 03 04:32:55 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	206832 kb
Host	smart-7b2dd9e2-222d-4715-84af-08abe7ec7214
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=725174372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.725174372
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3460462799
Short name	T162
Test name
Test status
Simulation time	156631228 ps
CPU time	2.04 seconds
Started	Aug 03 04:33:01 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	215388 kb
Host	smart-891442d0-d72e-4c7f-936e-23e3c41ffdd6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460462799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.3460462799
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1709536215
Short name	T48
Test name
Test status
Simulation time	80813045 ps
CPU time	1.01 seconds
Started	Aug 03 04:32:59 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	207000 kb
Host	smart-e98defb8-a1e2-4e80-8b05-00f9f0580dea
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1709536215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1709536215
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3694511759
Short name	T152
Test name
Test status
Simulation time	53222909 ps
CPU time	0.73 seconds
Started	Aug 03 04:32:55 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	206764 kb
Host	smart-34d1b4da-a47a-4dfe-b3b6-227534c2191d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3694511759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3694511759
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4056002574
Short name	T154
Test name
Test status
Simulation time	166535050 ps
CPU time	2.36 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	215300 kb
Host	smart-53652878-c0fb-4054-b2a8-de256931f5b4
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4056002574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4056002574
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.3394679351
Short name	T86
Test name
Test status
Simulation time	376765260 ps
CPU time	2.95 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	206972 kb
Host	smart-cb666f96-f10b-4aaf-8dc6-398cc1787a3f
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3394679351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.3394679351
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3636969214
Short name	T146
Test name
Test status
Simulation time	170822367 ps
CPU time	1.6 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	207112 kb
Host	smart-b4eded12-8b56-4dca-ad0a-f173d31eb629
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3636969214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3636969214
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.451886284
Short name	T143
Test name
Test status
Simulation time	163709076 ps
CPU time	2.22 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	207028 kb
Host	smart-210318fb-8141-46d3-b67d-6a6c32ec7413
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=451886284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.451886284
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1387981978
Short name	T81
Test name
Test status
Simulation time	289984776 ps
CPU time	2.58 seconds
Started	Aug 03 04:32:59 PM PDT 24
Finished	Aug 03 04:33:02 PM PDT 24
Peak memory	207080 kb
Host	smart-272f28da-d4ca-40f6-a2f0-676514532783
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1387981978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1387981978
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1545510533
Short name	T39
Test name
Test status
Simulation time	73167783 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206704 kb
Host	smart-18364d2a-8a07-4685-86e6-4a9897599a54
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1545510533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1545510533
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2336936967
Short name	T2
Test name
Test status
Simulation time	81926288 ps
CPU time	0.82 seconds
Started	Aug 03 04:33:06 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	206704 kb
Host	smart-633acb6c-0946-42b2-88eb-43799c4d3f40
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2336936967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2336936967
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3542712731
Short name	T76
Test name
Test status
Simulation time	40106138 ps
CPU time	0.72 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206724 kb
Host	smart-29ba434e-52cf-4280-a54b-c6c00236bbc5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3542712731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3542712731
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.850845263
Short name	T119
Test name
Test status
Simulation time	114108694 ps
CPU time	0.85 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:03 PM PDT 24
Peak memory	206860 kb
Host	smart-30f3ad49-ab7f-4f7e-978b-275e5f2c7ac5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=850845263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.850845263
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.907209138
Short name	T16
Test name
Test status
Simulation time	38350408 ps
CPU time	0.73 seconds
Started	Aug 03 04:34:41 PM PDT 24
Finished	Aug 03 04:34:42 PM PDT 24
Peak memory	206764 kb
Host	smart-6473bd20-12bb-4db4-971a-300c513a7715
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=907209138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.907209138
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.1533266567
Short name	T75
Test name
Test status
Simulation time	90210583 ps
CPU time	0.77 seconds
Started	Aug 03 04:33:22 PM PDT 24
Finished	Aug 03 04:33:22 PM PDT 24
Peak memory	206752 kb
Host	smart-277b22cc-02f3-42f8-9873-505fd0fa907d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1533266567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1533266567
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.948023167
Short name	T98
Test name
Test status
Simulation time	60478591 ps
CPU time	0.76 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	206756 kb
Host	smart-4d584294-85e6-41b7-810b-487183e1798a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=948023167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.948023167
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3648753140
Short name	T105
Test name
Test status
Simulation time	40949375 ps
CPU time	0.74 seconds
Started	Aug 03 04:33:19 PM PDT 24
Finished	Aug 03 04:33:20 PM PDT 24
Peak memory	206748 kb
Host	smart-9de2184f-e9ab-4904-9d2e-414e0456fe21
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3648753140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3648753140
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.4193654773
Short name	T7
Test name
Test status
Simulation time	87281068 ps
CPU time	0.75 seconds
Started	Aug 03 04:33:12 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	206768 kb
Host	smart-4aceaac2-8eef-4e68-bc17-619256ce966d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4193654773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4193654773
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.34886206
Short name	T42
Test name
Test status
Simulation time	85397955 ps
CPU time	0.76 seconds
Started	Aug 03 04:33:20 PM PDT 24
Finished	Aug 03 04:33:21 PM PDT 24
Peak memory	206764 kb
Host	smart-a77a2c1e-f854-41be-8720-8cc4e05062ff
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=34886206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.34886206
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3413944587
Short name	T100
Test name
Test status
Simulation time	369505470 ps
CPU time	3.67 seconds
Started	Aug 03 04:32:51 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	207044 kb
Host	smart-17272eb1-4e35-4ea7-a6db-a08c33db78e1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3413944587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3413944587
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.788687184
Short name	T149
Test name
Test status
Simulation time	1349516957 ps
CPU time	8.45 seconds
Started	Aug 03 04:33:02 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	207092 kb
Host	smart-1b83c174-f370-4512-83b7-31ff1275d6b7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=788687184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.788687184
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.332041836
Short name	T139
Test name
Test status
Simulation time	170548943 ps
CPU time	1.85 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:09 PM PDT 24
Peak memory	223580 kb
Host	smart-ebfed89a-dcc3-4936-ac04-f4392c9f7f1e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332041836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev _csr_mem_rw_with_rand_reset.332041836
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1649025593
Short name	T113
Test name
Test status
Simulation time	66851051 ps
CPU time	0.99 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	206880 kb
Host	smart-45f13fce-ae7a-4bbc-8205-e0ab65d1f272
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1649025593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1649025593
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.406334151
Short name	T117
Test name
Test status
Simulation time	51315057 ps
CPU time	0.81 seconds
Started	Aug 03 04:32:48 PM PDT 24
Finished	Aug 03 04:32:49 PM PDT 24
Peak memory	206692 kb
Host	smart-69ddba4f-b176-406a-a0a7-49eb26e81276
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=406334151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.406334151
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2569380649
Short name	T26
Test name
Test status
Simulation time	153210002 ps
CPU time	2.15 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	215312 kb
Host	smart-d780ebd8-63d3-4dbd-ab40-4af964ce5ba3
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2569380649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2569380649
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.2260763884
Short name	T24
Test name
Test status
Simulation time	775261830 ps
CPU time	4.64 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:33:01 PM PDT 24
Peak memory	207008 kb
Host	smart-4acc240e-c8d8-4a3f-89d6-1b76a600be07
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2260763884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.2260763884
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3870442857
Short name	T175
Test name
Test status
Simulation time	144934864 ps
CPU time	1.84 seconds
Started	Aug 03 04:33:03 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	207136 kb
Host	smart-a0af9922-f4e3-424e-91ef-8619f76730cb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3870442857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3870442857
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3146643736
Short name	T57
Test name
Test status
Simulation time	102423349 ps
CPU time	2.27 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	207188 kb
Host	smart-62f5bde0-55de-4415-a597-45fc8b33f87d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3146643736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3146643736
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1729075300
Short name	T134
Test name
Test status
Simulation time	2225218157 ps
CPU time	6.22 seconds
Started	Aug 03 04:33:08 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	207300 kb
Host	smart-9673102b-e880-463a-8aaf-a65ed1791f78
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1729075300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1729075300
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.776738980
Short name	T137
Test name
Test status
Simulation time	70625482 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:15 PM PDT 24
Finished	Aug 03 04:33:16 PM PDT 24
Peak memory	206844 kb
Host	smart-477b00f8-26d8-4b19-a500-9b00fbf76aa8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=776738980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.776738980
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.587804548
Short name	T118
Test name
Test status
Simulation time	47823309 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:15 PM PDT 24
Finished	Aug 03 04:33:16 PM PDT 24
Peak memory	206744 kb
Host	smart-3064ce85-e9c7-4d6d-a790-8deb1acbe2d7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=587804548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.587804548
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.123306463
Short name	T155
Test name
Test status
Simulation time	85426049 ps
CPU time	0.77 seconds
Started	Aug 03 04:33:16 PM PDT 24
Finished	Aug 03 04:33:17 PM PDT 24
Peak memory	206736 kb
Host	smart-b68ad0e2-e68c-4874-9cea-adf9a82f3d2b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=123306463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.123306463
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1208553022
Short name	T87
Test name
Test status
Simulation time	63941838 ps
CPU time	0.74 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206752 kb
Host	smart-74a75f0f-3659-479d-91a9-d5d119d6a410
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1208553022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1208553022
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.885041359
Short name	T160
Test name
Test status
Simulation time	60825150 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:21 PM PDT 24
Finished	Aug 03 04:33:22 PM PDT 24
Peak memory	206764 kb
Host	smart-423e416e-a1fd-4d51-8d8a-51916b21f37e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=885041359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.885041359
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1289627629
Short name	T132
Test name
Test status
Simulation time	43976293 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:14 PM PDT 24
Finished	Aug 03 04:33:15 PM PDT 24
Peak memory	206684 kb
Host	smart-738c3b1e-3a2a-410d-a378-483b69aacdc7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1289627629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1289627629
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.142026539
Short name	T169
Test name
Test status
Simulation time	44017225 ps
CPU time	0.72 seconds
Started	Aug 03 04:33:12 PM PDT 24
Finished	Aug 03 04:33:13 PM PDT 24
Peak memory	206668 kb
Host	smart-95d65192-a1fa-4c2f-8916-a08858e35085
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=142026539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.142026539
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3112221459
Short name	T156
Test name
Test status
Simulation time	59921754 ps
CPU time	0.73 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206764 kb
Host	smart-c8e4e06a-8a93-4e09-ad89-0d2250e12bb6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3112221459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3112221459
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.4171064060
Short name	T123
Test name
Test status
Simulation time	47345048 ps
CPU time	0.71 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:10 PM PDT 24
Peak memory	206672 kb
Host	smart-f3ad7012-b213-4856-b89e-b6e53db361c8
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4171064060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4171064060
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.3529416516
Short name	T71
Test name
Test status
Simulation time	117590043 ps
CPU time	0.82 seconds
Started	Aug 03 04:33:13 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206768 kb
Host	smart-2ca8724e-0a89-4aaa-9d13-25d900ee1c23
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3529416516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.3529416516
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1812741794
Short name	T22
Test name
Test status
Simulation time	93188018 ps
CPU time	1.37 seconds
Started	Aug 03 04:32:52 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	223468 kb
Host	smart-f140dfb9-818e-4a8b-8e8b-3fe9911997c9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812741794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.1812741794
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1968701814
Short name	T46
Test name
Test status
Simulation time	81499480 ps
CPU time	1 seconds
Started	Aug 03 04:32:51 PM PDT 24
Finished	Aug 03 04:32:52 PM PDT 24
Peak memory	206856 kb
Host	smart-e607d02c-1ef9-4408-93a2-090a0faf80cb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1968701814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1968701814
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.1678268618
Short name	T93
Test name
Test status
Simulation time	100402215 ps
CPU time	0.76 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206764 kb
Host	smart-f1c34014-6aee-41fd-b7bf-b79fa42ae4dc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1678268618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.1678268618
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3717112063
Short name	T109
Test name
Test status
Simulation time	98719699 ps
CPU time	1.42 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207148 kb
Host	smart-25bbf446-a4be-4100-bf52-e471b32164bb
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3717112063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3717112063
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4115911335
Short name	T29
Test name
Test status
Simulation time	984283338 ps
CPU time	6.03 seconds
Started	Aug 03 04:33:00 PM PDT 24
Finished	Aug 03 04:33:06 PM PDT 24
Peak memory	207096 kb
Host	smart-485fb6ce-f3c5-4e6d-85cd-b39937efbba9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4115911335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.4115911335
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.533160790
Short name	T102
Test name
Test status
Simulation time	58217694 ps
CPU time	1.24 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	215256 kb
Host	smart-6c4e91bb-0173-4b02-bbca-4c74cec6543a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533160790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev _csr_mem_rw_with_rand_reset.533160790
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.959433874
Short name	T51
Test name
Test status
Simulation time	83815737 ps
CPU time	0.98 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	206828 kb
Host	smart-f0eddcee-8026-4c2c-a72b-6236698f7f11
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=959433874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.959433874
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.541317330
Short name	T110
Test name
Test status
Simulation time	33366771 ps
CPU time	0.69 seconds
Started	Aug 03 04:33:11 PM PDT 24
Finished	Aug 03 04:33:11 PM PDT 24
Peak memory	206756 kb
Host	smart-293ab99d-cc4a-4edb-ab84-3b4da2101c72
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=541317330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.541317330
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.525703421
Short name	T67
Test name
Test status
Simulation time	139984398 ps
CPU time	1.16 seconds
Started	Aug 03 04:33:10 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207076 kb
Host	smart-f90ec9a7-abb0-4ca7-a5d7-e0b0e1a23ead
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=525703421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.525703421
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3707455444
Short name	T124
Test name
Test status
Simulation time	107491460 ps
CPU time	3.04 seconds
Started	Aug 03 04:32:51 PM PDT 24
Finished	Aug 03 04:32:55 PM PDT 24
Peak memory	207040 kb
Host	smart-89e24d4a-0a35-4d6a-8c83-abc7c40d97b5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3707455444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3707455444
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1970243920
Short name	T30
Test name
Test status
Simulation time	1083454590 ps
CPU time	5.06 seconds
Started	Aug 03 04:32:52 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	207104 kb
Host	smart-0023b749-8b13-4bb5-a97c-86e000034e38
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1970243920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1970243920
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2802423900
Short name	T69
Test name
Test status
Simulation time	171087499 ps
CPU time	1.36 seconds
Started	Aug 03 04:33:05 PM PDT 24
Finished	Aug 03 04:33:07 PM PDT 24
Peak memory	215456 kb
Host	smart-5e4c521f-65ac-4a00-962a-95a7c5a24aa7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802423900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.2802423900
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.738451090
Short name	T32
Test name
Test status
Simulation time	142158082 ps
CPU time	1.06 seconds
Started	Aug 03 04:33:15 PM PDT 24
Finished	Aug 03 04:33:16 PM PDT 24
Peak memory	206932 kb
Host	smart-c49fb473-d960-48e1-a417-1b8ded503df5
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=738451090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.738451090
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1717997674
Short name	T97
Test name
Test status
Simulation time	57764902 ps
CPU time	0.74 seconds
Started	Aug 03 04:33:03 PM PDT 24
Finished	Aug 03 04:33:04 PM PDT 24
Peak memory	206712 kb
Host	smart-e77fd2b4-8d5b-4170-b7b9-f4d82fbc052a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1717997674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1717997674
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.3037877035
Short name	T96
Test name
Test status
Simulation time	188784343 ps
CPU time	1.64 seconds
Started	Aug 03 04:32:58 PM PDT 24
Finished	Aug 03 04:33:00 PM PDT 24
Peak memory	207068 kb
Host	smart-9c63cac9-8c34-4212-afd7-b6f67e4c232d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3037877035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.3037877035
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.106803117
Short name	T25
Test name
Test status
Simulation time	105142515 ps
CPU time	2.54 seconds
Started	Aug 03 04:33:15 PM PDT 24
Finished	Aug 03 04:33:18 PM PDT 24
Peak memory	215332 kb
Host	smart-542e245c-41ad-4f56-a8db-81340bae5ab1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=106803117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.106803117
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2636802564
Short name	T62
Test name
Test status
Simulation time	328475485 ps
CPU time	2.46 seconds
Started	Aug 03 04:33:09 PM PDT 24
Finished	Aug 03 04:33:12 PM PDT 24
Peak memory	207168 kb
Host	smart-ed95794e-036e-44c5-b8c5-5b958eba761f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2636802564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2636802564
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.506341475
Short name	T66
Test name
Test status
Simulation time	234284910 ps
CPU time	1.92 seconds
Started	Aug 03 04:32:56 PM PDT 24
Finished	Aug 03 04:32:58 PM PDT 24
Peak memory	215320 kb
Host	smart-ce5e7057-5989-455f-b132-4dbb7430c835
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506341475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev _csr_mem_rw_with_rand_reset.506341475
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.884606500
Short name	T85
Test name
Test status
Simulation time	59180539 ps
CPU time	0.82 seconds
Started	Aug 03 04:32:53 PM PDT 24
Finished	Aug 03 04:32:54 PM PDT 24
Peak memory	206816 kb
Host	smart-a285ca41-915c-4554-9ba4-385b504e9967
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=884606500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.884606500
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.1744003996
Short name	T101
Test name
Test status
Simulation time	55049917 ps
CPU time	0.75 seconds
Started	Aug 03 04:33:14 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206760 kb
Host	smart-912099d2-ba16-4071-bb27-9c424158e228
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1744003996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1744003996
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.824224441
Short name	T167
Test name
Test status
Simulation time	134677126 ps
CPU time	1.26 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	207304 kb
Host	smart-3d60b7dc-ebf0-4abd-ad92-94ae0b92a964
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=824224441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.824224441
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2768621084
Short name	T140
Test name
Test status
Simulation time	218135694 ps
CPU time	2.22 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:06 PM PDT 24
Peak memory	207100 kb
Host	smart-e4d8b144-7d4d-44e2-b8c2-0e993750809f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2768621084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2768621084
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2078082781
Short name	T144
Test name
Test status
Simulation time	72127635 ps
CPU time	1.46 seconds
Started	Aug 03 04:32:54 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	215276 kb
Host	smart-0cdfb796-69ec-466a-b94a-409f9650a7a8
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078082781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.2078082781
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.297213096
Short name	T55
Test name
Test status
Simulation time	60546074 ps
CPU time	1.01 seconds
Started	Aug 03 04:33:04 PM PDT 24
Finished	Aug 03 04:33:05 PM PDT 24
Peak memory	206924 kb
Host	smart-6d01c60a-8f7f-4e26-a20d-26609ca5188b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=297213096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.297213096
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.704938413
Short name	T126
Test name
Test status
Simulation time	36621959 ps
CPU time	0.72 seconds
Started	Aug 03 04:32:55 PM PDT 24
Finished	Aug 03 04:32:56 PM PDT 24
Peak memory	206772 kb
Host	smart-d0883e3d-34e0-4248-9caa-fe25e3f83a0a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=704938413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.704938413
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2064171124
Short name	T157
Test name
Test status
Simulation time	97806099 ps
CPU time	1.06 seconds
Started	Aug 03 04:33:07 PM PDT 24
Finished	Aug 03 04:33:08 PM PDT 24
Peak memory	206984 kb
Host	smart-6e0a1ea6-ead6-41c8-b487-abcc83139e77
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2064171124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2064171124
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.1952653568
Short name	T77
Test name
Test status
Simulation time	1226073726 ps
CPU time	5.36 seconds
Started	Aug 03 04:33:08 PM PDT 24
Finished	Aug 03 04:33:14 PM PDT 24
Peak memory	206980 kb
Host	smart-5dfba574-c0ff-46ec-934f-446fc5777f99
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1952653568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.1952653568
Directory	/workspace/9.usbdev_tl_intg_err/latest