Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	365	1		T2	8		T14	5		T7	5
all_pins[1]	365	1		T2	8		T14	5		T7	5
all_pins[2]	365	1		T2	8		T14	5		T7	5
all_pins[3]	365	1		T2	8		T14	5		T7	5
all_pins[4]	365	1		T2	8		T14	5		T7	5
all_pins[5]	365	1		T2	8		T14	5		T7	5
all_pins[6]	365	1		T2	8		T14	5		T7	5
all_pins[7]	365	1		T2	8		T14	5		T7	5
all_pins[8]	365	1		T2	8		T14	5		T7	5
all_pins[9]	365	1		T2	8		T14	5		T7	5
all_pins[10]	365	1		T2	8		T14	5		T7	5
all_pins[11]	365	1		T2	8		T14	5		T7	5
all_pins[12]	365	1		T2	8		T14	5		T7	5
all_pins[13]	365	1		T2	8		T14	5		T7	5
all_pins[14]	365	1		T2	8		T14	5		T7	5
all_pins[15]	365	1		T2	8		T14	5		T7	5
all_pins[16]	365	1		T2	8		T14	5		T7	5
all_pins[17]	365	1		T2	8		T14	5		T7	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10521	1		T2	231		T14	144		T7	141
values[0x1]	1159	1		T2	25		T14	16		T7	19
transitions[0x0=>0x1]	904	1		T2	24		T14	15		T7	16
transitions[0x1=>0x0]	904	1		T2	24		T14	15		T7	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	303	1		T2	6		T14	4		T7	4
all_pins[0]	values[0x1]	62	1		T2	2		T14	1		T7	1
all_pins[0]	transitions[0x0=>0x1]	51	1		T2	2		T14	1		T7	1
all_pins[0]	transitions[0x1=>0x0]	40	1		T2	2		T14	2		T7	2
all_pins[1]	values[0x0]	314	1		T2	6		T14	3		T7	3
all_pins[1]	values[0x1]	51	1		T2	2		T14	2		T7	2
all_pins[1]	transitions[0x0=>0x1]	36	1		T2	2		T14	2		T7	1
all_pins[1]	transitions[0x1=>0x0]	69	1		T7	1		T15	3		T16	1
all_pins[2]	values[0x0]	281	1		T2	8		T14	5		T7	3
all_pins[2]	values[0x1]	84	1		T7	2		T15	4		T16	1
all_pins[2]	transitions[0x0=>0x1]	59	1		T7	2		T15	2		T36	1
all_pins[2]	transitions[0x1=>0x0]	40	1		T2	1		T14	4		T16	2
all_pins[3]	values[0x0]	300	1		T2	7		T14	1		T7	5
all_pins[3]	values[0x1]	65	1		T2	1		T14	4		T15	2
all_pins[3]	transitions[0x0=>0x1]	50	1		T2	1		T14	4		T15	2
all_pins[3]	transitions[0x1=>0x0]	33	1		T2	2		T7	1		T36	1
all_pins[4]	values[0x0]	317	1		T2	6		T14	5		T7	4
all_pins[4]	values[0x1]	48	1		T2	2		T7	1		T16	2
all_pins[4]	transitions[0x0=>0x1]	32	1		T2	2		T7	1		T36	1
all_pins[4]	transitions[0x1=>0x0]	66	1		T7	2		T15	3		T16	1
all_pins[5]	values[0x0]	283	1		T2	8		T14	5		T7	3
all_pins[5]	values[0x1]	82	1		T7	2		T15	3		T16	3
all_pins[5]	transitions[0x0=>0x1]	59	1		T7	2		T15	2		T16	1
all_pins[5]	transitions[0x1=>0x0]	48	1		T15	1		T39	1		T41	2
all_pins[6]	values[0x0]	294	1		T2	8		T14	5		T7	5
all_pins[6]	values[0x1]	71	1		T15	2		T16	2		T39	1
all_pins[6]	transitions[0x0=>0x1]	62	1		T15	2		T16	2		T39	1
all_pins[6]	transitions[0x1=>0x0]	43	1		T2	4		T14	1		T41	3
all_pins[7]	values[0x0]	313	1		T2	4		T14	4		T7	5
all_pins[7]	values[0x1]	52	1		T2	4		T14	1		T41	3
all_pins[7]	transitions[0x0=>0x1]	41	1		T2	4		T14	1		T41	3
all_pins[7]	transitions[0x1=>0x0]	41	1		T15	1		T16	1		T36	2
all_pins[8]	values[0x0]	313	1		T2	8		T14	5		T7	5
all_pins[8]	values[0x1]	52	1		T15	1		T16	1		T36	2
all_pins[8]	transitions[0x0=>0x1]	42	1		T15	1		T16	1		T36	2
all_pins[8]	transitions[0x1=>0x0]	48	1		T2	2		T7	2		T15	3
all_pins[9]	values[0x0]	307	1		T2	6		T14	5		T7	3
all_pins[9]	values[0x1]	58	1		T2	2		T7	2		T15	3
all_pins[9]	transitions[0x0=>0x1]	42	1		T2	2		T7	2		T15	3
all_pins[9]	transitions[0x1=>0x0]	48	1		T14	1		T7	1		T39	2
all_pins[10]	values[0x0]	301	1		T2	8		T14	4		T7	4
all_pins[10]	values[0x1]	64	1		T14	1		T7	1		T39	2
all_pins[10]	transitions[0x0=>0x1]	52	1		T14	1		T39	2		T41	3
all_pins[10]	transitions[0x1=>0x0]	42	1		T2	2		T15	1		T16	1
all_pins[11]	values[0x0]	311	1		T2	6		T14	5		T7	4
all_pins[11]	values[0x1]	54	1		T2	2		T7	1		T15	1
all_pins[11]	transitions[0x0=>0x1]	40	1		T2	2		T7	1		T15	1
all_pins[11]	transitions[0x1=>0x0]	66	1		T2	2		T7	2		T15	2
all_pins[12]	values[0x0]	285	1		T2	6		T14	5		T7	3
all_pins[12]	values[0x1]	80	1		T2	2		T7	2		T15	2
all_pins[12]	transitions[0x0=>0x1]	64	1		T2	2		T7	2		T15	2
all_pins[12]	transitions[0x1=>0x0]	50	1		T2	1		T14	3		T15	4
all_pins[13]	values[0x0]	299	1		T2	7		T14	2		T7	5
all_pins[13]	values[0x1]	66	1		T2	1		T14	3		T15	4
all_pins[13]	transitions[0x0=>0x1]	55	1		T14	2		T15	4		T16	2
all_pins[13]	transitions[0x1=>0x0]	53	1		T2	1		T7	2		T15	1
all_pins[14]	values[0x0]	301	1		T2	6		T14	4		T7	3
all_pins[14]	values[0x1]	64	1		T2	2		T14	1		T7	2
all_pins[14]	transitions[0x0=>0x1]	44	1		T2	2		T14	1		T7	2
all_pins[14]	transitions[0x1=>0x0]	62	1		T2	1		T15	2		T36	2
all_pins[15]	values[0x0]	283	1		T2	7		T14	5		T7	5
all_pins[15]	values[0x1]	82	1		T2	1		T15	2		T36	3
all_pins[15]	transitions[0x0=>0x1]	63	1		T2	1		T15	2		T36	1
all_pins[15]	transitions[0x1=>0x0]	57	1		T2	3		T14	3		T7	2
all_pins[16]	values[0x0]	289	1		T2	5		T14	2		T7	3
all_pins[16]	values[0x1]	76	1		T2	3		T14	3		T7	2
all_pins[16]	transitions[0x0=>0x1]	64	1		T2	3		T14	3		T7	1
all_pins[16]	transitions[0x1=>0x0]	36	1		T2	1		T15	3		T16	2
all_pins[17]	values[0x0]	317	1		T2	7		T14	5		T7	4
all_pins[17]	values[0x1]	48	1		T2	1		T7	1		T15	3
all_pins[17]	transitions[0x0=>0x1]	48	1		T2	1		T7	1		T15	3