Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T2	7		T14	4		T7	4
all_values[1]	275	1		T2	7		T14	4		T7	4
all_values[2]	275	1		T2	7		T14	4		T7	4
all_values[3]	275	1		T2	7		T14	4		T7	4
all_values[4]	275	1		T2	7		T14	4		T7	4
all_values[5]	275	1		T2	7		T14	4		T7	4
all_values[6]	275	1		T2	7		T14	4		T7	4
all_values[7]	275	1		T2	7		T14	4		T7	4
all_values[8]	275	1		T2	7		T14	4		T7	4
all_values[9]	275	1		T2	7		T14	4		T7	4
all_values[10]	275	1		T2	7		T14	4		T7	4
all_values[11]	275	1		T2	7		T14	4		T7	4
all_values[12]	275	1		T2	7		T14	4		T7	4
all_values[13]	275	1		T2	7		T14	4		T7	4
all_values[14]	275	1		T2	7		T14	4		T7	4
all_values[15]	275	1		T2	7		T14	4		T7	4
all_values[16]	275	1		T2	7		T14	4		T7	4
all_values[17]	275	1		T2	7		T14	4		T7	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6543	1		T2	173		T14	100		T7	94
auto[1]	2257	1		T2	51		T14	28		T7	34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	6009	1		T2	145		T14	81		T7	89
auto[1]	2791	1		T2	79		T14	47		T7	39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	5187	1		T2	115		T14	67		T7	76
auto[1]	3613	1		T2	109		T14	61		T7	52

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	89	1		T2	2		T14	1		T7	3
all_values[0]	auto[0]	auto[1]	auto[0]	79	1		T14	1		T15	2		T16	3
all_values[0]	auto[1]	auto[0]	auto[1]	52	1		T2	2		T14	2		T7	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T2	3		T15	3		T16	1
all_values[1]	auto[0]	auto[0]	auto[0]	88	1		T2	3		T15	2		T16	1
all_values[1]	auto[0]	auto[1]	auto[0]	75	1		T2	2		T14	2		T7	2
all_values[1]	auto[1]	auto[0]	auto[1]	63	1		T2	1		T14	1		T15	3
all_values[1]	auto[1]	auto[1]	auto[1]	49	1		T2	1		T14	1		T7	2
all_values[2]	auto[0]	auto[0]	auto[0]	43	1		T14	1		T15	1		T36	2
all_values[2]	auto[0]	auto[0]	auto[1]	52	1		T2	3		T14	1		T15	1
all_values[2]	auto[0]	auto[1]	auto[0]	33	1		T14	1		T7	1		T15	1
all_values[2]	auto[0]	auto[1]	auto[1]	39	1		T7	1		T15	1		T38	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1		T2	4		T15	1		T16	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T14	1		T7	2		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	61	1		T2	1		T7	2		T15	3
all_values[3]	auto[0]	auto[0]	auto[1]	23	1		T2	2		T36	1		T41	1
all_values[3]	auto[0]	auto[1]	auto[0]	48	1		T7	2		T36	1		T38	2
all_values[3]	auto[0]	auto[1]	auto[1]	24	1		T14	2		T15	1		T16	1
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T2	2		T14	1		T15	1
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T2	2		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	auto[0]	65	1		T14	1		T15	1		T39	3
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T14	1		T7	1		T15	1
all_values[4]	auto[0]	auto[1]	auto[0]	54	1		T2	3		T7	2		T15	3
all_values[4]	auto[0]	auto[1]	auto[1]	17	1		T2	1		T16	1		T42	1
all_values[4]	auto[1]	auto[0]	auto[1]	59	1		T2	1		T14	1		T7	1
all_values[4]	auto[1]	auto[1]	auto[1]	49	1		T2	2		T14	1		T15	1
all_values[5]	auto[0]	auto[0]	auto[0]	53	1		T2	1		T14	1		T15	1
all_values[5]	auto[0]	auto[0]	auto[1]	33	1		T2	2		T7	1		T39	1
all_values[5]	auto[0]	auto[1]	auto[0]	42	1		T2	2		T14	2		T15	1
all_values[5]	auto[0]	auto[1]	auto[1]	34	1		T7	2		T15	1		T16	2
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T2	2		T14	1		T7	1
all_values[5]	auto[1]	auto[1]	auto[1]	59	1		T15	1		T16	2		T36	1
all_values[6]	auto[0]	auto[0]	auto[0]	54	1		T2	2		T14	1		T7	3
all_values[6]	auto[0]	auto[0]	auto[1]	25	1		T2	1		T14	1		T15	2
all_values[6]	auto[0]	auto[1]	auto[0]	50	1		T2	2		T16	2		T41	2
all_values[6]	auto[0]	auto[1]	auto[1]	29	1		T16	1		T39	1		T41	1
all_values[6]	auto[1]	auto[0]	auto[1]	63	1		T14	2		T7	1		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	54	1		T2	2		T15	2		T16	1
all_values[7]	auto[0]	auto[0]	auto[0]	85	1		T2	1		T15	4		T16	2
all_values[7]	auto[0]	auto[1]	auto[0]	81	1		T2	2		T14	3		T7	2
all_values[7]	auto[1]	auto[0]	auto[1]	62	1		T14	1		T7	2		T15	2
all_values[7]	auto[1]	auto[1]	auto[1]	47	1		T2	4		T15	1		T16	1
all_values[8]	auto[0]	auto[0]	auto[0]	92	1		T2	3		T14	1		T7	3
all_values[8]	auto[0]	auto[1]	auto[0]	73	1		T2	1		T15	5		T36	1
all_values[8]	auto[1]	auto[0]	auto[1]	60	1		T2	3		T14	3		T7	1
all_values[8]	auto[1]	auto[1]	auto[1]	50	1		T15	1		T16	2		T36	2
all_values[9]	auto[0]	auto[0]	auto[0]	60	1		T2	3		T39	3		T73	2
all_values[9]	auto[0]	auto[0]	auto[1]	32	1		T15	2		T36	1		T38	1
all_values[9]	auto[0]	auto[1]	auto[0]	41	1		T14	1		T38	1		T41	3
all_values[9]	auto[0]	auto[1]	auto[1]	20	1		T2	1		T7	1		T15	2
all_values[9]	auto[1]	auto[0]	auto[1]	63	1		T2	1		T14	3		T7	2
all_values[9]	auto[1]	auto[1]	auto[1]	59	1		T2	2		T7	1		T15	2
all_values[10]	auto[0]	auto[0]	auto[0]	74	1		T2	3		T7	2		T15	2
all_values[10]	auto[0]	auto[0]	auto[1]	19	1		T14	1		T15	1		T41	1
all_values[10]	auto[0]	auto[1]	auto[0]	48	1		T2	1		T7	1		T15	1
all_values[10]	auto[0]	auto[1]	auto[1]	31	1		T2	1		T39	1		T41	2
all_values[10]	auto[1]	auto[0]	auto[1]	57	1		T2	2		T14	2		T15	2
all_values[10]	auto[1]	auto[1]	auto[1]	46	1		T14	1		T7	1		T15	1
all_values[11]	auto[0]	auto[0]	auto[0]	67	1		T2	1		T15	2		T16	1
all_values[11]	auto[0]	auto[0]	auto[1]	31	1		T2	1		T14	1		T7	1
all_values[11]	auto[0]	auto[1]	auto[0]	51	1		T14	1		T15	2		T16	2
all_values[11]	auto[0]	auto[1]	auto[1]	22	1		T2	1		T36	1		T41	1
all_values[11]	auto[1]	auto[0]	auto[1]	61	1		T2	2		T14	2		T7	1
all_values[11]	auto[1]	auto[1]	auto[1]	43	1		T2	2		T7	2		T15	1
all_values[12]	auto[0]	auto[0]	auto[0]	62	1		T2	2		T7	2		T15	2
all_values[12]	auto[0]	auto[0]	auto[1]	28	1		T14	1		T39	1		T41	2
all_values[12]	auto[0]	auto[1]	auto[0]	32	1		T14	1		T15	1		T36	3
all_values[12]	auto[0]	auto[1]	auto[1]	30	1		T2	1		T7	1		T15	1
all_values[12]	auto[1]	auto[0]	auto[1]	67	1		T2	2		T14	1		T16	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1		T2	2		T14	1		T7	1
all_values[13]	auto[0]	auto[0]	auto[0]	53	1		T2	2		T7	2		T15	1
all_values[13]	auto[0]	auto[0]	auto[1]	31	1		T73	2		T74	1		T75	1
all_values[13]	auto[0]	auto[1]	auto[0]	44	1		T2	2		T7	2		T15	1
all_values[13]	auto[0]	auto[1]	auto[1]	31	1		T14	2		T15	2		T16	1
all_values[13]	auto[1]	auto[0]	auto[1]	72	1		T2	2		T14	1		T16	2
all_values[13]	auto[1]	auto[1]	auto[1]	44	1		T2	1		T14	1		T15	3
all_values[14]	auto[0]	auto[0]	auto[0]	64	1		T14	1		T7	1		T15	2
all_values[14]	auto[0]	auto[0]	auto[1]	29	1		T2	1		T16	1		T36	1
all_values[14]	auto[0]	auto[1]	auto[0]	49	1		T14	1		T15	2		T16	1
all_values[14]	auto[0]	auto[1]	auto[1]	27	1		T7	1		T41	1		T76	1
all_values[14]	auto[1]	auto[0]	auto[1]	53	1		T2	4		T14	1		T7	1
all_values[14]	auto[1]	auto[1]	auto[1]	53	1		T2	2		T14	1		T7	1
all_values[15]	auto[0]	auto[0]	auto[0]	51	1		T2	3		T14	2		T15	2
all_values[15]	auto[0]	auto[0]	auto[1]	23	1		T7	1		T16	1		T42	1
all_values[15]	auto[0]	auto[1]	auto[0]	50	1		T14	1		T16	1		T39	2
all_values[15]	auto[0]	auto[1]	auto[1]	34	1		T15	1		T36	1		T41	1
all_values[15]	auto[1]	auto[0]	auto[1]	58	1		T2	2		T14	1		T7	3
all_values[15]	auto[1]	auto[1]	auto[1]	59	1		T2	2		T15	2		T16	1
all_values[16]	auto[0]	auto[0]	auto[0]	49	1		T16	2		T41	2		T71	1
all_values[16]	auto[0]	auto[0]	auto[1]	31	1		T2	1		T7	1		T15	2
all_values[16]	auto[0]	auto[1]	auto[0]	40	1		T15	3		T41	1		T73	4
all_values[16]	auto[0]	auto[1]	auto[1]	28	1		T2	1		T14	1		T36	1
all_values[16]	auto[1]	auto[0]	auto[1]	60	1		T2	4		T14	2		T7	1
all_values[16]	auto[1]	auto[1]	auto[1]	67	1		T2	1		T14	1		T7	2
all_values[17]	auto[0]	auto[0]	auto[0]	97	1		T2	3		T14	2		T15	2
all_values[17]	auto[0]	auto[1]	auto[0]	62	1		T2	2		T7	3		T15	2
all_values[17]	auto[1]	auto[0]	auto[1]	72	1		T14	2		T16	1		T36	1
all_values[17]	auto[1]	auto[1]	auto[1]	44	1		T2	2		T7	1		T15	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal