Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	344	1		T6	2		T16	5		T12	5
all_values[1]	344	1		T6	2		T16	5		T12	5
all_values[2]	344	1		T6	2		T16	5		T12	5
all_values[3]	344	1		T6	2		T16	5		T12	5
all_values[4]	344	1		T6	2		T16	5		T12	5
all_values[5]	344	1		T6	2		T16	5		T12	5
all_values[6]	344	1		T6	2		T16	5		T12	5
all_values[7]	344	1		T6	2		T16	5		T12	5
all_values[8]	344	1		T6	2		T16	5		T12	5
all_values[9]	344	1		T6	2		T16	5		T12	5
all_values[10]	344	1		T6	2		T16	5		T12	5
all_values[11]	344	1		T6	2		T16	5		T12	5
all_values[12]	344	1		T6	2		T16	5		T12	5
all_values[13]	344	1		T6	2		T16	5		T12	5
all_values[14]	344	1		T6	2		T16	5		T12	5
all_values[15]	344	1		T6	2		T16	5		T12	5
all_values[16]	344	1		T6	2		T16	5		T12	5
all_values[17]	344	1		T6	2		T16	5		T12	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	8228	1		T6	64		T16	113		T12	112
auto[1]	2780	1		T16	47		T12	48		T13	86

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	8890	1		T6	63		T16	122		T12	116
auto[1]	2118	1		T6	1		T16	38		T12	44

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	138	1		T6	2		T16	2		T22	2
all_values[0]	auto[0]	auto[1]	44	1		T16	1		T15	1		T59	2
all_values[0]	auto[1]	auto[0]	106	1		T16	2		T12	4		T13	6
all_values[0]	auto[1]	auto[1]	56	1		T12	1		T13	1		T14	2
all_values[1]	auto[0]	auto[0]	127	1		T6	2		T16	2		T22	2
all_values[1]	auto[0]	auto[1]	56	1		T16	2		T13	2		T15	1
all_values[1]	auto[1]	auto[0]	112	1		T16	1		T12	4		T13	2
all_values[1]	auto[1]	auto[1]	49	1		T12	1		T13	2		T15	1
all_values[2]	auto[0]	auto[0]	116	1		T6	1		T16	3		T12	1
all_values[2]	auto[0]	auto[1]	87	1		T6	1		T16	2		T12	3
all_values[2]	auto[1]	auto[0]	73	1		T13	5		T14	3		T15	1
all_values[2]	auto[1]	auto[1]	68	1		T12	1		T13	1		T59	2
all_values[3]	auto[0]	auto[0]	143	1		T6	2		T16	1		T22	2
all_values[3]	auto[0]	auto[1]	59	1		T15	2		T59	5		T60	1
all_values[3]	auto[1]	auto[0]	69	1		T16	2		T12	2		T13	2
all_values[3]	auto[1]	auto[1]	73	1		T16	2		T12	3		T59	1
all_values[4]	auto[0]	auto[0]	136	1		T6	2		T12	3		T22	2
all_values[4]	auto[0]	auto[1]	58	1		T13	3		T59	2		T61	1
all_values[4]	auto[1]	auto[0]	86	1		T16	1		T12	1		T13	1
all_values[4]	auto[1]	auto[1]	64	1		T16	4		T12	1		T13	3
all_values[5]	auto[0]	auto[0]	140	1		T6	2		T16	2		T22	2
all_values[5]	auto[0]	auto[1]	49	1		T16	3		T13	1		T15	1
all_values[5]	auto[1]	auto[0]	95	1		T12	1		T13	6		T14	1
all_values[5]	auto[1]	auto[1]	60	1		T12	4		T13	1		T14	3
all_values[6]	auto[0]	auto[0]	104	1		T6	2		T16	1		T12	4
all_values[6]	auto[0]	auto[1]	71	1		T16	2		T13	1		T59	4
all_values[6]	auto[1]	auto[0]	98	1		T16	2		T12	1		T13	4
all_values[6]	auto[1]	auto[1]	71	1		T13	3		T15	2		T61	1
all_values[7]	auto[0]	auto[0]	146	1		T6	2		T16	2		T22	2
all_values[7]	auto[0]	auto[1]	42	1		T16	2		T12	1		T13	1
all_values[7]	auto[1]	auto[0]	108	1		T12	2		T13	2		T14	3
all_values[7]	auto[1]	auto[1]	48	1		T16	1		T12	2		T13	1
all_values[8]	auto[0]	auto[0]	138	1		T6	2		T12	2		T22	2
all_values[8]	auto[0]	auto[1]	51	1		T12	1		T14	1		T59	1
all_values[8]	auto[1]	auto[0]	102	1		T16	3		T13	5		T14	2
all_values[8]	auto[1]	auto[1]	53	1		T16	2		T12	2		T13	1
all_values[9]	auto[0]	auto[0]	125	1		T6	2		T16	1		T12	1
all_values[9]	auto[0]	auto[1]	69	1		T16	2		T12	2		T13	1
all_values[9]	auto[1]	auto[0]	83	1		T13	4		T14	1		T59	6
all_values[9]	auto[1]	auto[1]	67	1		T16	2		T12	2		T13	2
all_values[10]	auto[0]	auto[0]	143	1		T6	2		T16	1		T12	1
all_values[10]	auto[0]	auto[1]	46	1		T16	3		T14	1		T15	1
all_values[10]	auto[1]	auto[0]	106	1		T16	1		T12	4		T13	2
all_values[10]	auto[1]	auto[1]	49	1		T13	1		T14	3		T59	1
all_values[11]	auto[0]	auto[0]	135	1		T6	2		T16	1		T12	1
all_values[11]	auto[0]	auto[1]	62	1		T16	2		T12	3		T13	1
all_values[11]	auto[1]	auto[0]	86	1		T16	2		T12	1		T13	3
all_values[11]	auto[1]	auto[1]	61	1		T13	1		T15	3		T59	1
all_values[12]	auto[0]	auto[0]	119	1		T6	2		T16	4		T12	1
all_values[12]	auto[0]	auto[1]	64	1		T16	1		T12	2		T15	1
all_values[12]	auto[1]	auto[0]	111	1		T12	1		T13	5		T14	2
all_values[12]	auto[1]	auto[1]	50	1		T12	1		T14	3		T15	2
all_values[13]	auto[0]	auto[0]	119	1		T6	2		T12	1		T22	2
all_values[13]	auto[0]	auto[1]	80	1		T16	1		T12	4		T13	3
all_values[13]	auto[1]	auto[0]	93	1		T16	1		T13	3		T14	1
all_values[13]	auto[1]	auto[1]	52	1		T16	3		T13	1		T15	3
all_values[14]	auto[0]	auto[0]	115	1		T6	2		T16	1		T12	1
all_values[14]	auto[0]	auto[1]	57	1		T12	3		T13	2		T15	1
all_values[14]	auto[1]	auto[0]	118	1		T16	4		T12	1		T13	1
all_values[14]	auto[1]	auto[1]	54	1		T13	5		T14	2		T59	1
all_values[15]	auto[0]	auto[0]	133	1		T6	2		T12	1		T22	2
all_values[15]	auto[0]	auto[1]	71	1		T12	2		T13	2		T15	2
all_values[15]	auto[1]	auto[0]	97	1		T16	3		T13	4		T14	1
all_values[15]	auto[1]	auto[1]	43	1		T16	2		T12	2		T61	3
all_values[16]	auto[0]	auto[0]	124	1		T6	2		T22	2		T23	2
all_values[16]	auto[0]	auto[1]	70	1		T13	2		T59	4		T61	1
all_values[16]	auto[1]	auto[0]	92	1		T16	5		T12	5		T13	2
all_values[16]	auto[1]	auto[1]	58	1		T13	3		T14	2		T15	2
all_values[17]	auto[0]	auto[0]	133	1		T6	2		T16	1		T12	2
all_values[17]	auto[0]	auto[1]	42	1		T12	2		T13	1		T59	3
all_values[17]	auto[1]	auto[0]	105	1		T16	3		T13	2		T14	3
all_values[17]	auto[1]	auto[1]	64	1		T16	1		T12	1		T13	1