| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 60.90 | 65.32 | 59.58 | 86.57 | 0.00 | 69.84 | 97.77 | 47.24 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 52.89 | 52.89 | 62.10 | 62.10 | 51.01 | 51.01 | 86.38 | 86.38 | 0.00 | 0.00 | 63.21 | 63.21 | 93.58 | 93.58 | 13.94 | 13.94 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.431039023 |
| 57.00 | 4.11 | 62.80 | 0.70 | 52.08 | 1.07 | 90.14 | 3.76 | 0.00 | 0.00 | 63.21 | 0.00 | 93.58 | 0.00 | 37.19 | 23.26 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4211990801 |
| 59.56 | 2.56 | 65.22 | 2.42 | 57.69 | 5.61 | 93.31 | 3.17 | 0.00 | 0.00 | 69.56 | 6.35 | 93.85 | 0.28 | 37.29 | 0.09 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.782872790 |
| 60.68 | 1.12 | 65.28 | 0.06 | 58.99 | 1.30 | 94.37 | 1.06 | 0.00 | 0.00 | 69.68 | 0.12 | 95.81 | 1.96 | 40.63 | 3.35 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4218957787 |
| 61.17 | 0.49 | 65.28 | 0.00 | 58.99 | 0.00 | 94.37 | 0.00 | 0.00 | 0.00 | 69.68 | 0.00 | 95.81 | 0.00 | 44.07 | 3.44 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.275289365 |
| 61.59 | 0.42 | 65.32 | 0.04 | 59.09 | 0.09 | 95.07 | 0.70 | 0.00 | 0.00 | 69.76 | 0.08 | 95.81 | 0.00 | 46.06 | 1.99 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.721861188 |
| 61.83 | 0.24 | 65.32 | 0.00 | 59.09 | 0.00 | 95.07 | 0.00 | 0.00 | 0.00 | 69.76 | 0.00 | 97.49 | 1.68 | 46.06 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3817396659 |
| 61.92 | 0.09 | 65.32 | 0.00 | 59.11 | 0.02 | 95.07 | 0.00 | 0.00 | 0.00 | 69.76 | 0.00 | 97.49 | 0.00 | 46.70 | 0.63 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2325291456 |
| 61.97 | 0.05 | 65.32 | 0.00 | 59.20 | 0.09 | 95.07 | 0.00 | 0.00 | 0.00 | 69.76 | 0.00 | 97.77 | 0.28 | 46.70 | 0.00 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3606077045 |
| 62.03 | 0.05 | 65.32 | 0.00 | 59.25 | 0.05 | 95.31 | 0.23 | 0.00 | 0.00 | 69.84 | 0.08 | 97.77 | 0.00 | 46.70 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1363911016 |
| 62.08 | 0.05 | 65.32 | 0.00 | 59.25 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 47.06 | 0.36 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3173300613 |
| 62.11 | 0.04 | 65.32 | 0.00 | 59.51 | 0.26 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 47.06 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2906947301 |
| 62.14 | 0.03 | 65.32 | 0.00 | 59.51 | 0.00 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 47.24 | 0.18 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2460529324 |
| 62.15 | 0.01 | 65.32 | 0.00 | 59.55 | 0.05 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 47.24 | 0.00 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1654694622 |
| 62.15 | 0.01 | 65.32 | 0.00 | 59.58 | 0.02 | 95.31 | 0.00 | 0.00 | 0.00 | 69.84 | 0.00 | 97.77 | 0.00 | 47.24 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1995459129 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3538068651 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3818245862 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4127333282 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4085329787 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1685162806 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.697698996 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2643600010 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2574571226 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.731264742 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3171768643 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2079880636 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3227636847 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3897527381 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2693059903 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3411877246 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1985157256 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.21028678 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1753201945 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2594706320 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1024874410 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2859402648 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3203774186 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3027148534 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1738678646 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1893150558 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4186402202 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3156334141 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3489154782 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2125282123 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1020589402 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2415829094 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3454013961 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1858063011 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1453755210 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.96923721 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1648835518 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1340214993 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1094234186 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3097990653 |
| /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.115273596 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1484973948 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1118370685 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.580292850 |
| /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2548689308 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4097273031 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1436564665 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.339020425 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.470219772 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3804662256 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2877945983 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2024868989 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4019191084 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3030044351 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.948674622 |
| /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1980141174 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3796007461 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.588348147 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2185942050 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1110347494 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1264741420 |
| /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2991248389 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.192581292 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3335814608 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.69295471 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1654936506 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3605144906 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3381969057 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1049265152 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.387878837 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1500291073 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3306737794 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.68658177 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3053262053 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2121761110 |
| /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1036147289 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3375064972 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2724207538 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1059051941 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2853443041 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4029429613 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3601716464 |
| /workspace/coverage/cover_reg_top/21.usbdev_intr_test.668678340 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2652168975 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3927770526 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3109280257 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2485052787 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2911116478 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1713866630 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.245866646 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2118667944 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.314028231 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1164469480 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.241855540 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3613504742 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1308407239 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.163381021 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1214021086 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.876789673 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1178827240 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4057271212 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2909556030 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.138393958 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1093151269 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1829405386 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1611594084 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2852709836 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1684376273 |
| /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1741956259 |
| /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2978402152 |
| /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3880602300 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2146724077 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3629299543 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1854774231 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1229074809 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2978858356 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2396904629 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4085841059 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1136061115 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3462810068 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1917260001 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.286442515 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2366723099 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3651748306 |
| /workspace/coverage/cover_reg_top/43.usbdev_intr_test.389737737 |
| /workspace/coverage/cover_reg_top/44.usbdev_intr_test.752469920 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.964880055 |
| /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2006059771 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3149429520 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3473575779 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.107938388 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3473637088 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.814541621 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2634558799 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2947169022 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3400642852 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1143707500 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.388655193 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1444970276 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1795047323 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4159174586 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.985649502 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.759637279 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.938098958 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4205048585 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.168693389 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.154975314 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3076279981 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.915277558 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.958767202 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2618239918 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1109081421 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3383662686 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4092752205 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2616396622 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2022224635 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2841217885 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3598733248 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3496833962 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2899883843 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2793896644 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1444970276 | Aug 04 04:32:37 PM PDT 24 | Aug 04 04:32:38 PM PDT 24 | 73245330 ps | ||
| T2 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.470219772 | Aug 04 04:31:34 PM PDT 24 | Aug 04 04:31:36 PM PDT 24 | 231234498 ps | ||
| T3 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.431039023 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 812360994 ps | ||
| T6 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4218957787 | Aug 04 04:32:57 PM PDT 24 | Aug 04 04:33:00 PM PDT 24 | 292053232 ps | ||
| T18 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3817396659 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 74414456 ps | ||
| T17 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3605144906 | Aug 04 04:31:43 PM PDT 24 | Aug 04 04:31:44 PM PDT 24 | 84157298 ps | ||
| T4 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3053262053 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:38 PM PDT 24 | 93510811 ps | ||
| T5 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3473637088 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 81986681 ps | ||
| T19 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3606077045 | Aug 04 04:31:32 PM PDT 24 | Aug 04 04:31:33 PM PDT 24 | 55236156 ps | ||
| T20 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1094234186 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 73164057 ps | ||
| T16 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.138393958 | Aug 04 04:31:31 PM PDT 24 | Aug 04 04:31:31 PM PDT 24 | 33114526 ps | ||
| T28 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.814541621 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 74651334 ps | ||
| T21 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2079880636 | Aug 04 04:32:51 PM PDT 24 | Aug 04 04:32:53 PM PDT 24 | 164163666 ps | ||
| T12 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2852709836 | Aug 04 04:31:33 PM PDT 24 | Aug 04 04:31:33 PM PDT 24 | 50214995 ps | ||
| T31 | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2121761110 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 59234903 ps | ||
| T32 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.68658177 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 248664762 ps | ||
| T47 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.314028231 | Aug 04 04:31:27 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 75188470 ps | ||
| T33 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3462810068 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 72557391 ps | ||
| T26 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.759637279 | Aug 04 04:32:55 PM PDT 24 | Aug 04 04:32:58 PM PDT 24 | 469933453 ps | ||
| T22 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2853443041 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:34 PM PDT 24 | 363994666 ps | ||
| T23 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4057271212 | Aug 04 04:31:18 PM PDT 24 | Aug 04 04:31:22 PM PDT 24 | 157906243 ps | ||
| T34 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1453755210 | Aug 04 04:31:28 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 93233694 ps | ||
| T24 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1214021086 | Aug 04 04:31:34 PM PDT 24 | Aug 04 04:31:36 PM PDT 24 | 108626381 ps | ||
| T30 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2616396622 | Aug 04 04:31:27 PM PDT 24 | Aug 04 04:31:32 PM PDT 24 | 826882792 ps | ||
| T13 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4211990801 | Aug 04 04:31:46 PM PDT 24 | Aug 04 04:31:47 PM PDT 24 | 49244064 ps | ||
| T25 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1893150558 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 100163885 ps | ||
| T35 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2841217885 | Aug 04 04:31:47 PM PDT 24 | Aug 04 04:31:48 PM PDT 24 | 102542258 ps | ||
| T27 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2906947301 | Aug 04 04:31:35 PM PDT 24 | Aug 04 04:31:38 PM PDT 24 | 151708228 ps | ||
| T14 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.389737737 | Aug 04 04:31:39 PM PDT 24 | Aug 04 04:31:40 PM PDT 24 | 42337426 ps | ||
| T15 | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2634558799 | Aug 04 04:31:40 PM PDT 24 | Aug 04 04:31:40 PM PDT 24 | 38091408 ps | ||
| T36 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2978858356 | Aug 04 04:31:31 PM PDT 24 | Aug 04 04:31:32 PM PDT 24 | 92706464 ps | ||
| T29 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1738678646 | Aug 04 04:32:44 PM PDT 24 | Aug 04 04:32:49 PM PDT 24 | 672088366 ps | ||
| T73 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1136061115 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 542483823 ps | ||
| T48 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1917260001 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 157652945 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4029429613 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 844739774 ps | ||
| T59 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2366723099 | Aug 04 04:31:40 PM PDT 24 | Aug 04 04:31:41 PM PDT 24 | 69935558 ps | ||
| T7 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.782872790 | Aug 04 04:32:39 PM PDT 24 | Aug 04 04:32:40 PM PDT 24 | 71343244 ps | ||
| T74 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1049265152 | Aug 04 04:31:56 PM PDT 24 | Aug 04 04:31:57 PM PDT 24 | 112456043 ps | ||
| T56 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3496833962 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 265507414 ps | ||
| T53 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1500291073 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 525853614 ps | ||
| T60 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3097990653 | Aug 04 04:32:53 PM PDT 24 | Aug 04 04:32:54 PM PDT 24 | 49039939 ps | ||
| T75 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.154975314 | Aug 04 04:31:31 PM PDT 24 | Aug 04 04:31:32 PM PDT 24 | 143318584 ps | ||
| T76 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.115273596 | Aug 04 04:32:24 PM PDT 24 | Aug 04 04:32:26 PM PDT 24 | 273199021 ps | ||
| T49 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2899883843 | Aug 04 04:31:19 PM PDT 24 | Aug 04 04:31:21 PM PDT 24 | 133345235 ps | ||
| T69 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.721861188 | Aug 04 04:31:42 PM PDT 24 | Aug 04 04:31:47 PM PDT 24 | 810945330 ps | ||
| T54 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1995459129 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 102769636 ps | ||
| T77 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2909556030 | Aug 04 04:31:27 PM PDT 24 | Aug 04 04:31:30 PM PDT 24 | 844766579 ps | ||
| T37 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3454013961 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:36 PM PDT 24 | 52492853 ps | ||
| T50 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1436564665 | Aug 04 04:33:01 PM PDT 24 | Aug 04 04:33:03 PM PDT 24 | 70708366 ps | ||
| T8 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3171768643 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 76307403 ps | ||
| T61 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1741956259 | Aug 04 04:31:54 PM PDT 24 | Aug 04 04:31:54 PM PDT 24 | 44820938 ps | ||
| T62 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3173300613 | Aug 04 04:31:46 PM PDT 24 | Aug 04 04:31:47 PM PDT 24 | 41481717 ps | ||
| T57 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.339020425 | Aug 04 04:31:57 PM PDT 24 | Aug 04 04:32:02 PM PDT 24 | 796510114 ps | ||
| T63 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2325291456 | Aug 04 04:32:23 PM PDT 24 | Aug 04 04:32:25 PM PDT 24 | 54439434 ps | ||
| T38 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3227636847 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 108984878 ps | ||
| T65 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3598733248 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 47645416 ps | ||
| T67 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1713866630 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 44909302 ps | ||
| T78 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.388655193 | Aug 04 04:31:34 PM PDT 24 | Aug 04 04:31:36 PM PDT 24 | 156734563 ps | ||
| T79 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2146724077 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 184738089 ps | ||
| T64 | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.275289365 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:38 PM PDT 24 | 65712612 ps | ||
| T58 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3818245862 | Aug 04 04:31:20 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 778586291 ps | ||
| T80 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3109280257 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 133651631 ps | ||
| T39 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3538068651 | Aug 04 04:32:52 PM PDT 24 | Aug 04 04:32:55 PM PDT 24 | 322214117 ps | ||
| T66 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.668678340 | Aug 04 04:31:32 PM PDT 24 | Aug 04 04:31:33 PM PDT 24 | 66308853 ps | ||
| T81 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2024868989 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:40 PM PDT 24 | 198177444 ps | ||
| T52 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2415829094 | Aug 04 04:33:10 PM PDT 24 | Aug 04 04:33:11 PM PDT 24 | 105303260 ps | ||
| T71 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2460529324 | Aug 04 04:32:58 PM PDT 24 | Aug 04 04:33:02 PM PDT 24 | 588926929 ps | ||
| T40 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3306737794 | Aug 04 04:32:35 PM PDT 24 | Aug 04 04:32:39 PM PDT 24 | 353286932 ps | ||
| T82 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1059051941 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:22 PM PDT 24 | 194050544 ps | ||
| T83 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3927770526 | Aug 04 04:31:51 PM PDT 24 | Aug 04 04:31:51 PM PDT 24 | 44846945 ps | ||
| T51 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.985649502 | Aug 04 04:31:35 PM PDT 24 | Aug 04 04:31:37 PM PDT 24 | 240763862 ps | ||
| T41 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.697698996 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:32 PM PDT 24 | 193688285 ps | ||
| T84 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3489154782 | Aug 04 04:32:55 PM PDT 24 | Aug 04 04:32:57 PM PDT 24 | 52035827 ps | ||
| T85 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4205048585 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 169993623 ps | ||
| T86 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1036147289 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:43 PM PDT 24 | 43486622 ps | ||
| T87 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.588348147 | Aug 04 04:31:50 PM PDT 24 | Aug 04 04:31:53 PM PDT 24 | 275829753 ps | ||
| T88 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4127333282 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 110848459 ps | ||
| T89 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2125282123 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 109336457 ps | ||
| T90 | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1685162806 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 122152036 ps | ||
| T9 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1363911016 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 67502105 ps | ||
| T91 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2548689308 | Aug 04 04:31:49 PM PDT 24 | Aug 04 04:31:50 PM PDT 24 | 40400941 ps | ||
| T92 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3880602300 | Aug 04 04:31:41 PM PDT 24 | Aug 04 04:31:42 PM PDT 24 | 66094182 ps | ||
| T93 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1308407239 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 100421736 ps | ||
| T94 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3335814608 | Aug 04 04:31:50 PM PDT 24 | Aug 04 04:31:52 PM PDT 24 | 198730832 ps | ||
| T95 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3796007461 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:32 PM PDT 24 | 68381303 ps | ||
| T70 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1020589402 | Aug 04 04:32:58 PM PDT 24 | Aug 04 04:33:04 PM PDT 24 | 981949036 ps | ||
| T96 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2022224635 | Aug 04 04:31:41 PM PDT 24 | Aug 04 04:31:43 PM PDT 24 | 69826402 ps | ||
| T97 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3381969057 | Aug 04 04:31:53 PM PDT 24 | Aug 04 04:31:54 PM PDT 24 | 87283998 ps | ||
| T98 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3383662686 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 134815689 ps | ||
| T99 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1143707500 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:45 PM PDT 24 | 570641689 ps | ||
| T100 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1340214993 | Aug 04 04:32:56 PM PDT 24 | Aug 04 04:32:59 PM PDT 24 | 96828687 ps | ||
| T101 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.938098958 | Aug 04 04:31:20 PM PDT 24 | Aug 04 04:31:21 PM PDT 24 | 83469952 ps | ||
| T102 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3897527381 | Aug 04 04:31:19 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 228503117 ps | ||
| T72 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2793896644 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:30 PM PDT 24 | 832584064 ps | ||
| T103 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2594706320 | Aug 04 04:31:28 PM PDT 24 | Aug 04 04:31:30 PM PDT 24 | 354663884 ps | ||
| T104 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3076279981 | Aug 04 04:31:28 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 78919087 ps | ||
| T105 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.107938388 | Aug 04 04:31:20 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 67437794 ps | ||
| T106 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1178827240 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 96359311 ps | ||
| T11 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.241855540 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:24 PM PDT 24 | 53799675 ps | ||
| T107 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1118370685 | Aug 04 04:33:00 PM PDT 24 | Aug 04 04:33:02 PM PDT 24 | 83447752 ps | ||
| T108 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.21028678 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 187968551 ps | ||
| T42 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3629299543 | Aug 04 04:32:58 PM PDT 24 | Aug 04 04:33:05 PM PDT 24 | 643917864 ps | ||
| T109 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1654936506 | Aug 04 04:31:59 PM PDT 24 | Aug 04 04:32:00 PM PDT 24 | 78032722 ps | ||
| T110 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1985157256 | Aug 04 04:31:18 PM PDT 24 | Aug 04 04:31:21 PM PDT 24 | 1180060685 ps | ||
| T111 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2978402152 | Aug 04 04:31:39 PM PDT 24 | Aug 04 04:31:40 PM PDT 24 | 41263735 ps | ||
| T55 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2693059903 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 125758691 ps | ||
| T10 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1854774231 | Aug 04 04:31:43 PM PDT 24 | Aug 04 04:31:44 PM PDT 24 | 160396255 ps | ||
| T112 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1795047323 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:31 PM PDT 24 | 64332901 ps | ||
| T46 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.731264742 | Aug 04 04:31:16 PM PDT 24 | Aug 04 04:31:18 PM PDT 24 | 104522404 ps | ||
| T43 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3375064972 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 188956137 ps | ||
| T44 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.948674622 | Aug 04 04:31:46 PM PDT 24 | Aug 04 04:31:48 PM PDT 24 | 118787643 ps | ||
| T45 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1164469480 | Aug 04 04:31:31 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 979413579 ps | ||
| T113 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4085841059 | Aug 04 04:31:36 PM PDT 24 | Aug 04 04:31:38 PM PDT 24 | 215183940 ps | ||
| T114 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2185942050 | Aug 04 04:31:47 PM PDT 24 | Aug 04 04:31:50 PM PDT 24 | 516347804 ps | ||
| T115 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.915277558 | Aug 04 04:32:33 PM PDT 24 | Aug 04 04:32:35 PM PDT 24 | 490074316 ps | ||
| T116 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.958767202 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 109979946 ps | ||
| T117 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1229074809 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 103194197 ps | ||
| T118 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.876789673 | Aug 04 04:32:51 PM PDT 24 | Aug 04 04:32:55 PM PDT 24 | 157136820 ps | ||
| T119 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2991248389 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:43 PM PDT 24 | 38048589 ps | ||
| T120 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3203774186 | Aug 04 04:32:25 PM PDT 24 | Aug 04 04:32:26 PM PDT 24 | 76575066 ps | ||
| T121 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1829405386 | Aug 04 04:32:06 PM PDT 24 | Aug 04 04:32:07 PM PDT 24 | 42049507 ps | ||
| T122 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2574571226 | Aug 04 04:31:23 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 1038337226 ps | ||
| T123 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.580292850 | Aug 04 04:31:47 PM PDT 24 | Aug 04 04:31:48 PM PDT 24 | 68684790 ps | ||
| T124 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1648835518 | Aug 04 04:33:02 PM PDT 24 | Aug 04 04:33:04 PM PDT 24 | 288988502 ps | ||
| T125 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2859402648 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:22 PM PDT 24 | 66167463 ps | ||
| T126 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1684376273 | Aug 04 04:31:41 PM PDT 24 | Aug 04 04:31:42 PM PDT 24 | 44749185 ps | ||
| T127 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4019191084 | Aug 04 04:31:42 PM PDT 24 | Aug 04 04:31:45 PM PDT 24 | 500945658 ps | ||
| T128 | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2652168975 | Aug 04 04:31:42 PM PDT 24 | Aug 04 04:31:43 PM PDT 24 | 74270241 ps | ||
| T129 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3804662256 | Aug 04 04:32:57 PM PDT 24 | Aug 04 04:32:58 PM PDT 24 | 111399270 ps | ||
| T130 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1264741420 | Aug 04 04:31:28 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 57166769 ps | ||
| T131 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1753201945 | Aug 04 04:31:33 PM PDT 24 | Aug 04 04:31:34 PM PDT 24 | 122799891 ps | ||
| T132 | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.245866646 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 73472083 ps | ||
| T133 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3027148534 | Aug 04 04:31:41 PM PDT 24 | Aug 04 04:31:44 PM PDT 24 | 319179094 ps | ||
| T134 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1858063011 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:22 PM PDT 24 | 55342761 ps | ||
| T135 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4097273031 | Aug 04 04:31:47 PM PDT 24 | Aug 04 04:31:48 PM PDT 24 | 117631042 ps | ||
| T136 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.387878837 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 191138259 ps | ||
| T137 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.752469920 | Aug 04 04:31:55 PM PDT 24 | Aug 04 04:31:56 PM PDT 24 | 55403553 ps | ||
| T138 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.163381021 | Aug 04 04:31:19 PM PDT 24 | Aug 04 04:31:20 PM PDT 24 | 61276330 ps | ||
| T139 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1110347494 | Aug 04 04:31:48 PM PDT 24 | Aug 04 04:31:50 PM PDT 24 | 196882429 ps | ||
| T140 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2643600010 | Aug 04 04:31:21 PM PDT 24 | Aug 04 04:31:25 PM PDT 24 | 258122502 ps | ||
| T141 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3601716464 | Aug 04 04:31:51 PM PDT 24 | Aug 04 04:31:51 PM PDT 24 | 53157738 ps | ||
| T142 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1654694622 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 240079813 ps | ||
| T143 | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1093151269 | Aug 04 04:31:41 PM PDT 24 | Aug 04 04:31:42 PM PDT 24 | 54642952 ps | ||
| T144 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2911116478 | Aug 04 04:31:48 PM PDT 24 | Aug 04 04:31:49 PM PDT 24 | 63561804 ps | ||
| T145 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.192581292 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 125013958 ps | ||
| T146 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2485052787 | Aug 04 04:31:49 PM PDT 24 | Aug 04 04:31:50 PM PDT 24 | 45950742 ps | ||
| T147 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3651748306 | Aug 04 04:31:38 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 45529712 ps | ||
| T148 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.286442515 | Aug 04 04:31:43 PM PDT 24 | Aug 04 04:31:46 PM PDT 24 | 447073066 ps | ||
| T149 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2877945983 | Aug 04 04:33:00 PM PDT 24 | Aug 04 04:33:01 PM PDT 24 | 37573794 ps | ||
| T150 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3030044351 | Aug 04 04:31:32 PM PDT 24 | Aug 04 04:31:35 PM PDT 24 | 106238844 ps | ||
| T151 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3400642852 | Aug 04 04:31:36 PM PDT 24 | Aug 04 04:31:38 PM PDT 24 | 100496846 ps | ||
| T152 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1611594084 | Aug 04 04:31:27 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 48270290 ps | ||
| T153 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1024874410 | Aug 04 04:32:07 PM PDT 24 | Aug 04 04:32:10 PM PDT 24 | 90483493 ps | ||
| T154 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1109081421 | Aug 04 04:31:28 PM PDT 24 | Aug 04 04:31:29 PM PDT 24 | 41724992 ps | ||
| T155 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1484973948 | Aug 04 04:32:56 PM PDT 24 | Aug 04 04:32:59 PM PDT 24 | 273204976 ps | ||
| T156 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4186402202 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 141950642 ps | ||
| T157 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3149429520 | Aug 04 04:31:27 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 38392446 ps | ||
| T158 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4085329787 | Aug 04 04:31:16 PM PDT 24 | Aug 04 04:31:17 PM PDT 24 | 89096188 ps | ||
| T159 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2006059771 | Aug 04 04:31:39 PM PDT 24 | Aug 04 04:31:39 PM PDT 24 | 44813287 ps | ||
| T160 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2724207538 | Aug 04 04:31:24 PM PDT 24 | Aug 04 04:31:26 PM PDT 24 | 394012851 ps | ||
| T161 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3473575779 | Aug 04 04:31:53 PM PDT 24 | Aug 04 04:31:54 PM PDT 24 | 38499849 ps | ||
| T162 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.168693389 | Aug 04 04:31:22 PM PDT 24 | Aug 04 04:31:23 PM PDT 24 | 42790005 ps | ||
| T163 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3411877246 | Aug 04 04:32:50 PM PDT 24 | Aug 04 04:32:52 PM PDT 24 | 252431743 ps | ||
| T164 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4159174586 | Aug 04 04:31:19 PM PDT 24 | Aug 04 04:31:22 PM PDT 24 | 184076926 ps | ||
| T165 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2118667944 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:31 PM PDT 24 | 49026011 ps | ||
| T166 | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2396904629 | Aug 04 04:32:58 PM PDT 24 | Aug 04 04:32:59 PM PDT 24 | 87011925 ps | ||
| T167 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2618239918 | Aug 04 04:31:30 PM PDT 24 | Aug 04 04:31:31 PM PDT 24 | 68987075 ps | ||
| T168 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.964880055 | Aug 04 04:32:03 PM PDT 24 | Aug 04 04:32:04 PM PDT 24 | 81358803 ps | ||
| T169 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3156334141 | Aug 04 04:31:45 PM PDT 24 | Aug 04 04:31:46 PM PDT 24 | 41414936 ps | ||
| T170 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.69295471 | Aug 04 04:31:52 PM PDT 24 | Aug 04 04:31:56 PM PDT 24 | 1223549419 ps | ||
| T171 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3613504742 | Aug 04 04:31:26 PM PDT 24 | Aug 04 04:31:28 PM PDT 24 | 79030611 ps | ||
| T172 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4092752205 | Aug 04 04:31:37 PM PDT 24 | Aug 04 04:31:41 PM PDT 24 | 254283778 ps | ||
| T173 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1980141174 | Aug 04 04:32:57 PM PDT 24 | Aug 04 04:32:58 PM PDT 24 | 45234785 ps | ||
| T174 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.96923721 | Aug 04 04:32:59 PM PDT 24 | Aug 04 04:33:02 PM PDT 24 | 233143927 ps | ||
| T175 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2947169022 | Aug 04 04:31:25 PM PDT 24 | Aug 04 04:31:27 PM PDT 24 | 155787099 ps |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.431039023 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 812360994 ps |
| CPU time | 4.24 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207068 kb |
| Host | smart-44e1b48e-364f-40ea-8ee2-ec62b03ff93e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=431039023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.431039023 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4211990801 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 49244064 ps |
| CPU time | 0.71 seconds |
| Started | Aug 04 04:31:46 PM PDT 24 |
| Finished | Aug 04 04:31:47 PM PDT 24 |
| Peak memory | 206744 kb |
| Host | smart-a8322a10-94fc-4502-9def-7bb6e0ac9b6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4211990801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4211990801 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.782872790 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 71343244 ps |
| CPU time | 0.78 seconds |
| Started | Aug 04 04:32:39 PM PDT 24 |
| Finished | Aug 04 04:32:40 PM PDT 24 |
| Peak memory | 206816 kb |
| Host | smart-9b0816bf-6fee-4300-90bc-2bf90e371a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=782872790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.782872790 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4218957787 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 292053232 ps |
| CPU time | 2.79 seconds |
| Started | Aug 04 04:32:57 PM PDT 24 |
| Finished | Aug 04 04:33:00 PM PDT 24 |
| Peak memory | 207012 kb |
| Host | smart-4d46f38c-9a31-42a0-842a-c3c25360267e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4218957787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4218957787 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.275289365 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 65712612 ps |
| CPU time | 0.73 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:38 PM PDT 24 |
| Peak memory | 206712 kb |
| Host | smart-1ea9bef8-3976-4b7e-ad12-a8785be98d6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=275289365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.275289365 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.721861188 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 810945330 ps |
| CPU time | 4.62 seconds |
| Started | Aug 04 04:31:42 PM PDT 24 |
| Finished | Aug 04 04:31:47 PM PDT 24 |
| Peak memory | 207116 kb |
| Host | smart-56835a6b-ab62-441f-bef9-151d375ed8bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=721861188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.721861188 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3817396659 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 74414456 ps |
| CPU time | 1.35 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 207052 kb |
| Host | smart-9bd5e07c-caa1-431b-885d-c232d7db2155 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3817396659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3817396659 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2325291456 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 54439434 ps |
| CPU time | 0.87 seconds |
| Started | Aug 04 04:32:23 PM PDT 24 |
| Finished | Aug 04 04:32:25 PM PDT 24 |
| Peak memory | 205716 kb |
| Host | smart-b2f3cc5e-1668-433e-b876-e77eeb0bd452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2325291456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2325291456 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3606077045 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 55236156 ps |
| CPU time | 0.98 seconds |
| Started | Aug 04 04:31:32 PM PDT 24 |
| Finished | Aug 04 04:31:33 PM PDT 24 |
| Peak memory | 207080 kb |
| Host | smart-95915c52-af87-41ec-9c0c-90c5227bc540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3606077045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3606077045 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1363911016 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 67502105 ps |
| CPU time | 0.8 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 206956 kb |
| Host | smart-1abb2bd6-68b7-43f5-9053-aa5b4ce68739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1363911016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1363911016 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3173300613 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 41481717 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:31:46 PM PDT 24 |
| Finished | Aug 04 04:31:47 PM PDT 24 |
| Peak memory | 206672 kb |
| Host | smart-21a0fc04-53c3-4020-9a20-7616e7133f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3173300613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3173300613 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2906947301 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 151708228 ps |
| CPU time | 2.88 seconds |
| Started | Aug 04 04:31:35 PM PDT 24 |
| Finished | Aug 04 04:31:38 PM PDT 24 |
| Peak memory | 220368 kb |
| Host | smart-0dec2553-6194-4295-835b-ffbd53dfc117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2906947301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2906947301 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2460529324 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 588926929 ps |
| CPU time | 3.94 seconds |
| Started | Aug 04 04:32:58 PM PDT 24 |
| Finished | Aug 04 04:33:02 PM PDT 24 |
| Peak memory | 207060 kb |
| Host | smart-3a3f5a06-6ebd-44d4-a2b5-7ece763a6bc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2460529324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2460529324 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1654694622 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 240079813 ps |
| CPU time | 3.11 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 215332 kb |
| Host | smart-9fcb3f3b-d478-4e7c-afb0-9c9f98b75baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1654694622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1654694622 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1995459129 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 102769636 ps |
| CPU time | 1.34 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207092 kb |
| Host | smart-49de44a3-2090-46cc-abae-00fc10c0ead5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1995459129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1995459129 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3538068651 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 322214117 ps |
| CPU time | 3.39 seconds |
| Started | Aug 04 04:32:52 PM PDT 24 |
| Finished | Aug 04 04:32:55 PM PDT 24 |
| Peak memory | 207052 kb |
| Host | smart-67b15546-a001-407b-a47e-308c14118f0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3538068651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3538068651 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3818245862 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 778586291 ps |
| CPU time | 4.11 seconds |
| Started | Aug 04 04:31:20 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 207116 kb |
| Host | smart-9088e479-366b-4543-8bf5-d3134f6559e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3818245862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3818245862 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.4127333282 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 110848459 ps |
| CPU time | 2.15 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 215316 kb |
| Host | smart-ee912d24-1905-43a4-9874-dd10e0eaedbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127333282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.4127333282 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.4085329787 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 89096188 ps |
| CPU time | 0.96 seconds |
| Started | Aug 04 04:31:16 PM PDT 24 |
| Finished | Aug 04 04:31:17 PM PDT 24 |
| Peak memory | 206904 kb |
| Host | smart-c190177f-7e45-4041-8270-c7638c741a00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4085329787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.4085329787 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1685162806 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 122152036 ps |
| CPU time | 0.85 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 206748 kb |
| Host | smart-d47ef8c5-2b23-4d52-9ca7-69a3e4c8c6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1685162806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1685162806 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.697698996 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 193688285 ps |
| CPU time | 2.25 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:32 PM PDT 24 |
| Peak memory | 215212 kb |
| Host | smart-66cc27aa-59c9-49b4-823a-1a62a3a2d793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=697698996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.697698996 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2643600010 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 258122502 ps |
| CPU time | 2.41 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 207040 kb |
| Host | smart-88c62ecb-b433-4fa2-a34f-5b8dda5ecd37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2643600010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2643600010 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.2574571226 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1038337226 ps |
| CPU time | 4.58 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 207140 kb |
| Host | smart-4b038ef9-f8d6-478a-a61e-e5e261dd1481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2574571226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.2574571226 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.731264742 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 104522404 ps |
| CPU time | 1.96 seconds |
| Started | Aug 04 04:31:16 PM PDT 24 |
| Finished | Aug 04 04:31:18 PM PDT 24 |
| Peak memory | 207024 kb |
| Host | smart-d23597fb-db9d-4448-840d-46cc2a0d0b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=731264742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.731264742 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3171768643 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 76307403 ps |
| CPU time | 0.85 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206876 kb |
| Host | smart-f49172ea-e71e-477b-a6ea-77174eaad180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3171768643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3171768643 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2079880636 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 164163666 ps |
| CPU time | 1.93 seconds |
| Started | Aug 04 04:32:51 PM PDT 24 |
| Finished | Aug 04 04:32:53 PM PDT 24 |
| Peak memory | 215280 kb |
| Host | smart-79b8852a-c659-443f-b329-d51464d56dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079880636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.2079880636 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3227636847 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 108984878 ps |
| CPU time | 1.03 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206784 kb |
| Host | smart-1d670bda-7073-4f64-8fcf-51f879767294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3227636847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3227636847 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3897527381 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 228503117 ps |
| CPU time | 3.92 seconds |
| Started | Aug 04 04:31:19 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206988 kb |
| Host | smart-9438f9d7-db53-40a3-bc34-8db872d160dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3897527381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3897527381 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2693059903 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 125758691 ps |
| CPU time | 1.05 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207076 kb |
| Host | smart-c3b31356-429b-432e-ae94-aeb16a6a9029 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2693059903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2693059903 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3411877246 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 252431743 ps |
| CPU time | 2.18 seconds |
| Started | Aug 04 04:32:50 PM PDT 24 |
| Finished | Aug 04 04:32:52 PM PDT 24 |
| Peak memory | 215280 kb |
| Host | smart-b663ad7a-2844-452a-b8d4-4eff00ddfcb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3411877246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3411877246 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1985157256 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 1180060685 ps |
| CPU time | 3.53 seconds |
| Started | Aug 04 04:31:18 PM PDT 24 |
| Finished | Aug 04 04:31:21 PM PDT 24 |
| Peak memory | 207120 kb |
| Host | smart-da37f746-81f4-4dd3-a887-5cebac83c339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1985157256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1985157256 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.21028678 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 187968551 ps |
| CPU time | 1.76 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 223664 kb |
| Host | smart-c1da18bf-5600-4678-b8bc-fcf851353071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21028678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev _csr_mem_rw_with_rand_reset.21028678 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1753201945 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 122799891 ps |
| CPU time | 0.95 seconds |
| Started | Aug 04 04:31:33 PM PDT 24 |
| Finished | Aug 04 04:31:34 PM PDT 24 |
| Peak memory | 206940 kb |
| Host | smart-b553cfa6-70a1-47e8-a48c-57d10b9a24df |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1753201945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1753201945 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2594706320 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 354663884 ps |
| CPU time | 1.7 seconds |
| Started | Aug 04 04:31:28 PM PDT 24 |
| Finished | Aug 04 04:31:30 PM PDT 24 |
| Peak memory | 207108 kb |
| Host | smart-a0578479-8c1a-4f48-87be-faa87a0839e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2594706320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2594706320 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1024874410 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 90483493 ps |
| CPU time | 2.46 seconds |
| Started | Aug 04 04:32:07 PM PDT 24 |
| Finished | Aug 04 04:32:10 PM PDT 24 |
| Peak memory | 215224 kb |
| Host | smart-17647cab-909e-436b-9a0a-df17275468fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024874410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.1024874410 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2859402648 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 66167463 ps |
| CPU time | 0.92 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:22 PM PDT 24 |
| Peak memory | 206852 kb |
| Host | smart-fae9a4a5-181a-4285-ad77-95f2575afc28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2859402648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2859402648 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3203774186 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 76575066 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:32:25 PM PDT 24 |
| Finished | Aug 04 04:32:26 PM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-b112f042-d885-499f-b2da-3e848fe511a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3203774186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3203774186 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3027148534 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 319179094 ps |
| CPU time | 3.04 seconds |
| Started | Aug 04 04:31:41 PM PDT 24 |
| Finished | Aug 04 04:31:44 PM PDT 24 |
| Peak memory | 207128 kb |
| Host | smart-e247f965-ab0e-4975-a1d7-a5aa01c8f9ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3027148534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3027148534 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1738678646 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 672088366 ps |
| CPU time | 4.29 seconds |
| Started | Aug 04 04:32:44 PM PDT 24 |
| Finished | Aug 04 04:32:49 PM PDT 24 |
| Peak memory | 207024 kb |
| Host | smart-a72c55e5-c831-4abe-a780-90cf37294b3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1738678646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1738678646 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1893150558 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 100163885 ps |
| CPU time | 2.41 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 215252 kb |
| Host | smart-13bea436-957e-483f-bfaa-9903a4d5abf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893150558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd ev_csr_mem_rw_with_rand_reset.1893150558 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4186402202 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 141950642 ps |
| CPU time | 1.06 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 206872 kb |
| Host | smart-d79fa0f2-a30e-466e-b3e2-5d166bbc9bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4186402202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4186402202 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.3156334141 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 41414936 ps |
| CPU time | 0.71 seconds |
| Started | Aug 04 04:31:45 PM PDT 24 |
| Finished | Aug 04 04:31:46 PM PDT 24 |
| Peak memory | 206856 kb |
| Host | smart-5b8026fa-d819-4cfc-9cca-471c9e97bea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3156334141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.3156334141 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3489154782 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 52035827 ps |
| CPU time | 0.96 seconds |
| Started | Aug 04 04:32:55 PM PDT 24 |
| Finished | Aug 04 04:32:57 PM PDT 24 |
| Peak memory | 207020 kb |
| Host | smart-c611af87-565c-4e25-8a17-621a73c13739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3489154782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3489154782 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2125282123 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 109336457 ps |
| CPU time | 1.53 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207104 kb |
| Host | smart-67d8202b-2113-4672-9a7d-24f3c1506daf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2125282123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2125282123 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1020589402 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 981949036 ps |
| CPU time | 5.06 seconds |
| Started | Aug 04 04:32:58 PM PDT 24 |
| Finished | Aug 04 04:33:04 PM PDT 24 |
| Peak memory | 206992 kb |
| Host | smart-75a5849e-11d6-4302-9d58-516899c132b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1020589402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1020589402 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2415829094 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 105303260 ps |
| CPU time | 1.24 seconds |
| Started | Aug 04 04:33:10 PM PDT 24 |
| Finished | Aug 04 04:33:11 PM PDT 24 |
| Peak memory | 215288 kb |
| Host | smart-69b79fad-a2d1-482b-ab8a-3bb188e29751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415829094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.2415829094 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3454013961 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 52492853 ps |
| CPU time | 0.96 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:36 PM PDT 24 |
| Peak memory | 206872 kb |
| Host | smart-76458da5-e3ae-4c24-86ac-9fe285e4f684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3454013961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3454013961 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1858063011 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 55342761 ps |
| CPU time | 0.68 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:22 PM PDT 24 |
| Peak memory | 206712 kb |
| Host | smart-bc87beb4-a1eb-44a6-ba05-f47608a00b03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1858063011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1858063011 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1453755210 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 93233694 ps |
| CPU time | 1.11 seconds |
| Started | Aug 04 04:31:28 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 207100 kb |
| Host | smart-5645544c-d562-4b11-ac49-7725ab327533 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1453755210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1453755210 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.96923721 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 233143927 ps |
| CPU time | 2.87 seconds |
| Started | Aug 04 04:32:59 PM PDT 24 |
| Finished | Aug 04 04:33:02 PM PDT 24 |
| Peak memory | 215284 kb |
| Host | smart-6f1d2483-7357-486b-89f8-0924a386145b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=96923721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.96923721 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1648835518 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 288988502 ps |
| CPU time | 2.47 seconds |
| Started | Aug 04 04:33:02 PM PDT 24 |
| Finished | Aug 04 04:33:04 PM PDT 24 |
| Peak memory | 207012 kb |
| Host | smart-336b5f35-34de-4a6b-b830-8f216b621e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1648835518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1648835518 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1340214993 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 96828687 ps |
| CPU time | 2.29 seconds |
| Started | Aug 04 04:32:56 PM PDT 24 |
| Finished | Aug 04 04:32:59 PM PDT 24 |
| Peak memory | 215260 kb |
| Host | smart-aea9111e-83ae-49e4-882f-341d8221e1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340214993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.1340214993 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1094234186 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 73164057 ps |
| CPU time | 0.83 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206916 kb |
| Host | smart-7342fa83-9235-4412-b34a-1f945763483d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1094234186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1094234186 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3097990653 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 49039939 ps |
| CPU time | 0.7 seconds |
| Started | Aug 04 04:32:53 PM PDT 24 |
| Finished | Aug 04 04:32:54 PM PDT 24 |
| Peak memory | 206664 kb |
| Host | smart-15376ecc-d5d0-4ee1-9237-e8db0ed041ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3097990653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3097990653 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.115273596 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 273199021 ps |
| CPU time | 1.83 seconds |
| Started | Aug 04 04:32:24 PM PDT 24 |
| Finished | Aug 04 04:32:26 PM PDT 24 |
| Peak memory | 206024 kb |
| Host | smart-634c8a48-3f91-4402-9a48-b49e81e914df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=115273596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.115273596 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.1484973948 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 273204976 ps |
| CPU time | 2.91 seconds |
| Started | Aug 04 04:32:56 PM PDT 24 |
| Finished | Aug 04 04:32:59 PM PDT 24 |
| Peak memory | 215220 kb |
| Host | smart-f1fefbeb-b599-431a-938b-fe411fc09244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1484973948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.1484973948 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1118370685 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 83447752 ps |
| CPU time | 1.58 seconds |
| Started | Aug 04 04:33:00 PM PDT 24 |
| Finished | Aug 04 04:33:02 PM PDT 24 |
| Peak memory | 215308 kb |
| Host | smart-c702e255-1c62-4caf-857b-34a51020bf30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118370685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.1118370685 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.580292850 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 68684790 ps |
| CPU time | 0.8 seconds |
| Started | Aug 04 04:31:47 PM PDT 24 |
| Finished | Aug 04 04:31:48 PM PDT 24 |
| Peak memory | 206832 kb |
| Host | smart-cc876352-9d8a-4f11-ae13-08662a1296ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=580292850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.580292850 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2548689308 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 40400941 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:31:49 PM PDT 24 |
| Finished | Aug 04 04:31:50 PM PDT 24 |
| Peak memory | 206764 kb |
| Host | smart-d09af564-dd59-4260-935f-191504ddae34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2548689308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2548689308 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4097273031 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 117631042 ps |
| CPU time | 1.06 seconds |
| Started | Aug 04 04:31:47 PM PDT 24 |
| Finished | Aug 04 04:31:48 PM PDT 24 |
| Peak memory | 207140 kb |
| Host | smart-eb08bafa-c1de-44ae-acfc-ba5d6590f3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4097273031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4097273031 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1436564665 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 70708366 ps |
| CPU time | 1.85 seconds |
| Started | Aug 04 04:33:01 PM PDT 24 |
| Finished | Aug 04 04:33:03 PM PDT 24 |
| Peak memory | 207068 kb |
| Host | smart-59ebf4c2-f55b-4d37-baaf-2838f0917929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1436564665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1436564665 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.339020425 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 796510114 ps |
| CPU time | 4.94 seconds |
| Started | Aug 04 04:31:57 PM PDT 24 |
| Finished | Aug 04 04:32:02 PM PDT 24 |
| Peak memory | 207020 kb |
| Host | smart-5636b69c-3565-4171-a2f1-6b0dee219537 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=339020425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.339020425 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.470219772 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 231234498 ps |
| CPU time | 1.87 seconds |
| Started | Aug 04 04:31:34 PM PDT 24 |
| Finished | Aug 04 04:31:36 PM PDT 24 |
| Peak memory | 215348 kb |
| Host | smart-9ef056c5-d8b7-4fcb-86d5-431302c774f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470219772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde v_csr_mem_rw_with_rand_reset.470219772 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3804662256 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 111399270 ps |
| CPU time | 0.85 seconds |
| Started | Aug 04 04:32:57 PM PDT 24 |
| Finished | Aug 04 04:32:58 PM PDT 24 |
| Peak memory | 206724 kb |
| Host | smart-63f426aa-5570-4d76-87fd-60cb2ffe6bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3804662256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3804662256 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2877945983 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 37573794 ps |
| CPU time | 0.67 seconds |
| Started | Aug 04 04:33:00 PM PDT 24 |
| Finished | Aug 04 04:33:01 PM PDT 24 |
| Peak memory | 206668 kb |
| Host | smart-97ed0909-8f44-44b3-8bf1-ff41a137a03c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2877945983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2877945983 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.2024868989 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 198177444 ps |
| CPU time | 1.61 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:40 PM PDT 24 |
| Peak memory | 207068 kb |
| Host | smart-ad121f98-3c13-4afd-b10a-ac7f68dc183b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2024868989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.2024868989 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.4019191084 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 500945658 ps |
| CPU time | 2.61 seconds |
| Started | Aug 04 04:31:42 PM PDT 24 |
| Finished | Aug 04 04:31:45 PM PDT 24 |
| Peak memory | 207092 kb |
| Host | smart-315c906a-c25a-4b0d-91bc-f70f2529e2c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4019191084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.4019191084 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3030044351 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 106238844 ps |
| CPU time | 2.76 seconds |
| Started | Aug 04 04:31:32 PM PDT 24 |
| Finished | Aug 04 04:31:35 PM PDT 24 |
| Peak memory | 215344 kb |
| Host | smart-e4735168-ab6e-40b3-83dd-dfd3d5f5617d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030044351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.3030044351 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.948674622 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 118787643 ps |
| CPU time | 1.01 seconds |
| Started | Aug 04 04:31:46 PM PDT 24 |
| Finished | Aug 04 04:31:48 PM PDT 24 |
| Peak memory | 206832 kb |
| Host | smart-a4ee27be-fe46-410b-aa54-d7f73e6a3fc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=948674622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.948674622 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1980141174 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 45234785 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:32:57 PM PDT 24 |
| Finished | Aug 04 04:32:58 PM PDT 24 |
| Peak memory | 206668 kb |
| Host | smart-13be508e-aa9c-49a9-9ffe-f5acbd8389c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1980141174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1980141174 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3796007461 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 68381303 ps |
| CPU time | 1.09 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:32 PM PDT 24 |
| Peak memory | 207004 kb |
| Host | smart-5738c213-1a07-4898-a1f9-9fa201ed89cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3796007461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3796007461 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.588348147 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 275829753 ps |
| CPU time | 2.7 seconds |
| Started | Aug 04 04:31:50 PM PDT 24 |
| Finished | Aug 04 04:31:53 PM PDT 24 |
| Peak memory | 215296 kb |
| Host | smart-5399a05c-fd3f-4dab-930d-fc4b42dca6ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=588348147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.588348147 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2185942050 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 516347804 ps |
| CPU time | 2.66 seconds |
| Started | Aug 04 04:31:47 PM PDT 24 |
| Finished | Aug 04 04:31:50 PM PDT 24 |
| Peak memory | 207104 kb |
| Host | smart-582224eb-def6-489f-8ee9-0617529e9a63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2185942050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2185942050 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1110347494 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 196882429 ps |
| CPU time | 1.9 seconds |
| Started | Aug 04 04:31:48 PM PDT 24 |
| Finished | Aug 04 04:31:50 PM PDT 24 |
| Peak memory | 218316 kb |
| Host | smart-fbb34069-a8ba-4d63-b64a-f847f96870bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110347494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1110347494 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1264741420 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 57166769 ps |
| CPU time | 0.84 seconds |
| Started | Aug 04 04:31:28 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 206804 kb |
| Host | smart-f81050ed-0b3b-4871-8787-3d272410c64a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1264741420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1264741420 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2991248389 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 38048589 ps |
| CPU time | 0.73 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:43 PM PDT 24 |
| Peak memory | 206820 kb |
| Host | smart-80812283-904f-4701-a608-1c14d10cd369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2991248389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2991248389 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.192581292 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 125013958 ps |
| CPU time | 1.08 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 207180 kb |
| Host | smart-7f40e48d-5bfd-4ee2-b359-45e80f9eed78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=192581292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.192581292 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.3335814608 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 198730832 ps |
| CPU time | 1.96 seconds |
| Started | Aug 04 04:31:50 PM PDT 24 |
| Finished | Aug 04 04:31:52 PM PDT 24 |
| Peak memory | 207120 kb |
| Host | smart-051b4678-3159-45fc-8efa-24a55b364343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3335814608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.3335814608 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.69295471 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1223549419 ps |
| CPU time | 3.75 seconds |
| Started | Aug 04 04:31:52 PM PDT 24 |
| Finished | Aug 04 04:31:56 PM PDT 24 |
| Peak memory | 207184 kb |
| Host | smart-d41cde0c-4856-446e-aa08-b1a58ef07199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=69295471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.69295471 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1654936506 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 78032722 ps |
| CPU time | 1.69 seconds |
| Started | Aug 04 04:31:59 PM PDT 24 |
| Finished | Aug 04 04:32:00 PM PDT 24 |
| Peak memory | 215356 kb |
| Host | smart-b4832aea-50c0-4fdf-88cd-a53cec7f97e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654936506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.1654936506 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3605144906 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 84157298 ps |
| CPU time | 0.82 seconds |
| Started | Aug 04 04:31:43 PM PDT 24 |
| Finished | Aug 04 04:31:44 PM PDT 24 |
| Peak memory | 206888 kb |
| Host | smart-60892058-faa6-463f-969a-a3f2910f3444 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3605144906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3605144906 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.3381969057 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 87283998 ps |
| CPU time | 0.83 seconds |
| Started | Aug 04 04:31:53 PM PDT 24 |
| Finished | Aug 04 04:31:54 PM PDT 24 |
| Peak memory | 206236 kb |
| Host | smart-1c72d4f8-d9cf-4629-aedf-91b8f0644e89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3381969057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3381969057 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1049265152 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 112456043 ps |
| CPU time | 1.51 seconds |
| Started | Aug 04 04:31:56 PM PDT 24 |
| Finished | Aug 04 04:31:57 PM PDT 24 |
| Peak memory | 207088 kb |
| Host | smart-a12629df-468c-4045-b843-fce0b54803a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1049265152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1049265152 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.387878837 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 191138259 ps |
| CPU time | 2.39 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 222992 kb |
| Host | smart-a2cb8c62-edd8-4b8e-9983-a4708bb17e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=387878837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.387878837 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1500291073 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 525853614 ps |
| CPU time | 2.67 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 207184 kb |
| Host | smart-ee3d83ce-82ef-4770-ad6f-ea41374667f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1500291073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1500291073 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.3306737794 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 353286932 ps |
| CPU time | 3.26 seconds |
| Started | Aug 04 04:32:35 PM PDT 24 |
| Finished | Aug 04 04:32:39 PM PDT 24 |
| Peak memory | 206972 kb |
| Host | smart-3dd17fe5-d202-40c0-84a0-42e4618328e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3306737794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.3306737794 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.68658177 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 248664762 ps |
| CPU time | 4.11 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 207128 kb |
| Host | smart-a3c6cdd7-6312-4e71-8147-65fa7a43a841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=68658177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.68658177 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.3053262053 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 93510811 ps |
| CPU time | 1.21 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:38 PM PDT 24 |
| Peak memory | 215096 kb |
| Host | smart-394b0284-d289-4870-ad50-e71c559bb145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053262053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.3053262053 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2121761110 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 59234903 ps |
| CPU time | 0.92 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-97c05938-56e8-403c-bf19-646a32736542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2121761110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2121761110 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.1036147289 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 43486622 ps |
| CPU time | 0.74 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:43 PM PDT 24 |
| Peak memory | 206780 kb |
| Host | smart-8685f02f-8b22-4956-84b8-1530561d1c49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1036147289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.1036147289 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3375064972 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 188956137 ps |
| CPU time | 2.18 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 206964 kb |
| Host | smart-d553538c-58ef-4590-a572-6393fb4c7389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3375064972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3375064972 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2724207538 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 394012851 ps |
| CPU time | 2.73 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 207040 kb |
| Host | smart-8cd3725b-2bbe-483f-979c-79b234689a16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2724207538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2724207538 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1059051941 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 194050544 ps |
| CPU time | 1.39 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:22 PM PDT 24 |
| Peak memory | 207092 kb |
| Host | smart-57dfe062-28e9-4a95-9442-9eff4f6ba895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1059051941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.1059051941 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2853443041 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 363994666 ps |
| CPU time | 3.58 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:34 PM PDT 24 |
| Peak memory | 223364 kb |
| Host | smart-0d393d99-4762-4d89-8703-cada7a3195d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2853443041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2853443041 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.4029429613 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 844739774 ps |
| CPU time | 2.98 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 207084 kb |
| Host | smart-5fec5662-2850-4e7c-919c-d7885a98a4b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4029429613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.4029429613 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.3601716464 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 53157738 ps |
| CPU time | 0.73 seconds |
| Started | Aug 04 04:31:51 PM PDT 24 |
| Finished | Aug 04 04:31:51 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-d249363b-81c7-473b-94e2-bc41f8ce6957 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3601716464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.3601716464 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.668678340 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 66308853 ps |
| CPU time | 0.71 seconds |
| Started | Aug 04 04:31:32 PM PDT 24 |
| Finished | Aug 04 04:31:33 PM PDT 24 |
| Peak memory | 206860 kb |
| Host | smart-01488cda-2277-4f50-b814-6b747ce6ab1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=668678340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.668678340 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2652168975 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 74270241 ps |
| CPU time | 0.77 seconds |
| Started | Aug 04 04:31:42 PM PDT 24 |
| Finished | Aug 04 04:31:43 PM PDT 24 |
| Peak memory | 206708 kb |
| Host | smart-1534b6b7-46f9-492b-b144-19706214eaea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2652168975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2652168975 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3927770526 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 44846945 ps |
| CPU time | 0.73 seconds |
| Started | Aug 04 04:31:51 PM PDT 24 |
| Finished | Aug 04 04:31:51 PM PDT 24 |
| Peak memory | 206720 kb |
| Host | smart-391bb643-4745-4839-8646-7eb235aac05c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3927770526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3927770526 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.3109280257 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 133651631 ps |
| CPU time | 0.77 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 206748 kb |
| Host | smart-78fc1a77-ef90-4794-8c17-df047ed9b09e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3109280257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.3109280257 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.2485052787 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 45950742 ps |
| CPU time | 0.67 seconds |
| Started | Aug 04 04:31:49 PM PDT 24 |
| Finished | Aug 04 04:31:50 PM PDT 24 |
| Peak memory | 206728 kb |
| Host | smart-ef80bcb3-e44d-4d68-8154-2a06e9d04f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2485052787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.2485052787 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.2911116478 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 63561804 ps |
| CPU time | 0.75 seconds |
| Started | Aug 04 04:31:48 PM PDT 24 |
| Finished | Aug 04 04:31:49 PM PDT 24 |
| Peak memory | 206700 kb |
| Host | smart-b2e08220-46b2-4d1e-af6f-29c2e5f5e3da |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2911116478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.2911116478 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1713866630 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 44909302 ps |
| CPU time | 0.68 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 206672 kb |
| Host | smart-ed7944e9-8bd1-4891-9eb5-aa08784ab84a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1713866630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1713866630 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.245866646 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 73472083 ps |
| CPU time | 0.74 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 206712 kb |
| Host | smart-9acf7d3f-8b8b-4542-a82c-363dea6f1078 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=245866646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.245866646 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2118667944 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 49026011 ps |
| CPU time | 0.7 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:31 PM PDT 24 |
| Peak memory | 206748 kb |
| Host | smart-9ea5640f-35ba-4a10-b360-e08b2aaa2c6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2118667944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2118667944 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.314028231 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 75188470 ps |
| CPU time | 1.81 seconds |
| Started | Aug 04 04:31:27 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 207104 kb |
| Host | smart-39484a47-8ec5-4f17-a19b-fa06ce6a0c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=314028231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.314028231 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1164469480 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 979413579 ps |
| CPU time | 7.39 seconds |
| Started | Aug 04 04:31:31 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 207084 kb |
| Host | smart-bbb7f09f-6e22-4d4c-a029-445fed45e3c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1164469480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1164469480 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.241855540 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 53799675 ps |
| CPU time | 0.78 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:24 PM PDT 24 |
| Peak memory | 206844 kb |
| Host | smart-7c7e7622-5849-4b08-ae75-8ea9aa8962fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=241855540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.241855540 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3613504742 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 79030611 ps |
| CPU time | 1.84 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 215480 kb |
| Host | smart-c59863ad-4f01-4f5e-9920-1f37475e9741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613504742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.3613504742 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1308407239 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 100421736 ps |
| CPU time | 1.06 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 206884 kb |
| Host | smart-48f8814d-f728-49d2-83fe-ee14318892ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1308407239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1308407239 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.163381021 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 61276330 ps |
| CPU time | 0.74 seconds |
| Started | Aug 04 04:31:19 PM PDT 24 |
| Finished | Aug 04 04:31:20 PM PDT 24 |
| Peak memory | 206772 kb |
| Host | smart-bf005a51-bbdb-4944-ac00-e972cd1aa35c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=163381021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.163381021 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.1214021086 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 108626381 ps |
| CPU time | 1.43 seconds |
| Started | Aug 04 04:31:34 PM PDT 24 |
| Finished | Aug 04 04:31:36 PM PDT 24 |
| Peak memory | 207024 kb |
| Host | smart-c8e7dd50-0e88-4efc-860c-6e3015c4f107 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1214021086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.1214021086 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.876789673 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 157136820 ps |
| CPU time | 3.59 seconds |
| Started | Aug 04 04:32:51 PM PDT 24 |
| Finished | Aug 04 04:32:55 PM PDT 24 |
| Peak memory | 206928 kb |
| Host | smart-1e47fe18-e56d-4643-a5b6-83896a566f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=876789673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.876789673 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1178827240 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 96359311 ps |
| CPU time | 1.17 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 207112 kb |
| Host | smart-263c8b1f-07ce-4ae9-a151-5ed2320702ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1178827240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1178827240 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.4057271212 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 157906243 ps |
| CPU time | 1.58 seconds |
| Started | Aug 04 04:31:18 PM PDT 24 |
| Finished | Aug 04 04:31:22 PM PDT 24 |
| Peak memory | 206996 kb |
| Host | smart-48f68c6b-4319-4cb8-88d6-4f20d308e1d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4057271212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.4057271212 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2909556030 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 844766579 ps |
| CPU time | 3.11 seconds |
| Started | Aug 04 04:31:27 PM PDT 24 |
| Finished | Aug 04 04:31:30 PM PDT 24 |
| Peak memory | 207196 kb |
| Host | smart-6060e5e4-572a-4fdb-93aa-609c92d2d776 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2909556030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2909556030 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.138393958 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 33114526 ps |
| CPU time | 0.66 seconds |
| Started | Aug 04 04:31:31 PM PDT 24 |
| Finished | Aug 04 04:31:31 PM PDT 24 |
| Peak memory | 206732 kb |
| Host | smart-775ed2df-6441-4760-a5d7-c128114f4017 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=138393958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.138393958 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1093151269 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 54642952 ps |
| CPU time | 0.74 seconds |
| Started | Aug 04 04:31:41 PM PDT 24 |
| Finished | Aug 04 04:31:42 PM PDT 24 |
| Peak memory | 206728 kb |
| Host | smart-f58f0dd3-dd2b-4086-9342-3facf1030b0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1093151269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1093151269 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.1829405386 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 42049507 ps |
| CPU time | 0.66 seconds |
| Started | Aug 04 04:32:06 PM PDT 24 |
| Finished | Aug 04 04:32:07 PM PDT 24 |
| Peak memory | 206760 kb |
| Host | smart-5c5ffcdb-3b54-4f77-8a06-2bd21ab4fa04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1829405386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.1829405386 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1611594084 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 48270290 ps |
| CPU time | 0.7 seconds |
| Started | Aug 04 04:31:27 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 206672 kb |
| Host | smart-df2f863b-31ef-44bf-abd5-e230b83a114b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1611594084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1611594084 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2852709836 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 50214995 ps |
| CPU time | 0.78 seconds |
| Started | Aug 04 04:31:33 PM PDT 24 |
| Finished | Aug 04 04:31:33 PM PDT 24 |
| Peak memory | 207072 kb |
| Host | smart-68eaf4f2-0edd-483f-90c0-798b28777640 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2852709836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2852709836 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1684376273 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 44749185 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:31:41 PM PDT 24 |
| Finished | Aug 04 04:31:42 PM PDT 24 |
| Peak memory | 206748 kb |
| Host | smart-f0c5ac38-dfdf-45f4-8584-594120ff81ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1684376273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1684376273 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1741956259 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 44820938 ps |
| CPU time | 0.78 seconds |
| Started | Aug 04 04:31:54 PM PDT 24 |
| Finished | Aug 04 04:31:54 PM PDT 24 |
| Peak memory | 206744 kb |
| Host | smart-288ec20c-d1cb-4bc8-90a4-b2f006a829cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1741956259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1741956259 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2978402152 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 41263735 ps |
| CPU time | 0.75 seconds |
| Started | Aug 04 04:31:39 PM PDT 24 |
| Finished | Aug 04 04:31:40 PM PDT 24 |
| Peak memory | 206740 kb |
| Host | smart-aed77f85-4f0c-458c-98d3-4c77438e8b08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2978402152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2978402152 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3880602300 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 66094182 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:31:41 PM PDT 24 |
| Finished | Aug 04 04:31:42 PM PDT 24 |
| Peak memory | 206732 kb |
| Host | smart-11e0c370-c936-40b5-a095-62d118de1037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3880602300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3880602300 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2146724077 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 184738089 ps |
| CPU time | 2.13 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:26 PM PDT 24 |
| Peak memory | 207236 kb |
| Host | smart-ebae40c5-8b2f-4cb3-add1-c04067c07360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2146724077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2146724077 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3629299543 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 643917864 ps |
| CPU time | 6.71 seconds |
| Started | Aug 04 04:32:58 PM PDT 24 |
| Finished | Aug 04 04:33:05 PM PDT 24 |
| Peak memory | 206844 kb |
| Host | smart-353139fd-4e44-4816-be83-52074e5f7990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3629299543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3629299543 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1854774231 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 160396255 ps |
| CPU time | 0.9 seconds |
| Started | Aug 04 04:31:43 PM PDT 24 |
| Finished | Aug 04 04:31:44 PM PDT 24 |
| Peak memory | 206832 kb |
| Host | smart-19792087-f6a3-47c5-82a1-8a7530e4d9d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1854774231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.1854774231 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.1229074809 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 103194197 ps |
| CPU time | 1.28 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 215316 kb |
| Host | smart-3434286b-f8ae-44ef-9b8b-0d7d83ddaadc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229074809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.1229074809 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2978858356 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 92706464 ps |
| CPU time | 0.81 seconds |
| Started | Aug 04 04:31:31 PM PDT 24 |
| Finished | Aug 04 04:31:32 PM PDT 24 |
| Peak memory | 206912 kb |
| Host | smart-3dafee1a-f3bd-46d1-a6d9-e34141b44638 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2978858356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2978858356 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.2396904629 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 87011925 ps |
| CPU time | 0.73 seconds |
| Started | Aug 04 04:32:58 PM PDT 24 |
| Finished | Aug 04 04:32:59 PM PDT 24 |
| Peak memory | 206424 kb |
| Host | smart-f1829291-4f01-425e-a625-7d62a3b89459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2396904629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.2396904629 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4085841059 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 215183940 ps |
| CPU time | 2.34 seconds |
| Started | Aug 04 04:31:36 PM PDT 24 |
| Finished | Aug 04 04:31:38 PM PDT 24 |
| Peak memory | 215292 kb |
| Host | smart-9ce768aa-12ce-4b5f-9509-617c173d454c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4085841059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4085841059 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1136061115 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 542483823 ps |
| CPU time | 4.3 seconds |
| Started | Aug 04 04:31:23 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 207028 kb |
| Host | smart-3a26ed0e-2809-4e64-8065-ab1027aac363 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1136061115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1136061115 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3462810068 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 72557391 ps |
| CPU time | 1.07 seconds |
| Started | Aug 04 04:31:26 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207148 kb |
| Host | smart-43275fb8-03dc-469a-b519-c83ca03b1790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3462810068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3462810068 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1917260001 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 157652945 ps |
| CPU time | 1.93 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 207232 kb |
| Host | smart-718196d4-f823-4ba4-b5ef-76496eb7324d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1917260001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1917260001 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.286442515 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 447073066 ps |
| CPU time | 2.84 seconds |
| Started | Aug 04 04:31:43 PM PDT 24 |
| Finished | Aug 04 04:31:46 PM PDT 24 |
| Peak memory | 207096 kb |
| Host | smart-be42354d-8f80-4276-a76e-41a135b7687b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=286442515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.286442515 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2366723099 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 69935558 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:31:40 PM PDT 24 |
| Finished | Aug 04 04:31:41 PM PDT 24 |
| Peak memory | 206848 kb |
| Host | smart-ac643402-a990-4f2f-8dc2-56547a661a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2366723099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2366723099 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3651748306 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 45529712 ps |
| CPU time | 0.81 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 206700 kb |
| Host | smart-2fd07137-4c37-4021-bf97-c59cd5c98932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3651748306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3651748306 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.389737737 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 42337426 ps |
| CPU time | 0.72 seconds |
| Started | Aug 04 04:31:39 PM PDT 24 |
| Finished | Aug 04 04:31:40 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-88f0a5d8-63d9-4869-bc58-285ce327d9d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=389737737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.389737737 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.752469920 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 55403553 ps |
| CPU time | 0.79 seconds |
| Started | Aug 04 04:31:55 PM PDT 24 |
| Finished | Aug 04 04:31:56 PM PDT 24 |
| Peak memory | 206740 kb |
| Host | smart-67ecf769-516d-4e9a-b5a6-217064461668 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=752469920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.752469920 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.964880055 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 81358803 ps |
| CPU time | 0.78 seconds |
| Started | Aug 04 04:32:03 PM PDT 24 |
| Finished | Aug 04 04:32:04 PM PDT 24 |
| Peak memory | 206772 kb |
| Host | smart-677bb9b2-74df-405e-99ea-a6a4a0630108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=964880055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.964880055 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2006059771 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 44813287 ps |
| CPU time | 0.7 seconds |
| Started | Aug 04 04:31:39 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 206764 kb |
| Host | smart-3b6afef3-6768-428a-9fce-2b62fc5e12e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2006059771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2006059771 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.3149429520 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 38392446 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:31:27 PM PDT 24 |
| Finished | Aug 04 04:31:28 PM PDT 24 |
| Peak memory | 206724 kb |
| Host | smart-383adc72-6628-49d8-b8d8-2b0a09b60be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3149429520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3149429520 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.3473575779 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 38499849 ps |
| CPU time | 0.71 seconds |
| Started | Aug 04 04:31:53 PM PDT 24 |
| Finished | Aug 04 04:31:54 PM PDT 24 |
| Peak memory | 206768 kb |
| Host | smart-6ff8efe4-7301-4a1c-87cb-8d62cb8f85e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3473575779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.3473575779 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.107938388 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 67437794 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:31:20 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 206788 kb |
| Host | smart-649bc0fa-7c72-4c2d-a25d-dd1a769389bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=107938388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.107938388 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.3473637088 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 81986681 ps |
| CPU time | 2.19 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 220300 kb |
| Host | smart-3bcf3d7a-a91f-4ffa-9c19-9dd5ff194380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473637088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.3473637088 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.814541621 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 74651334 ps |
| CPU time | 0.86 seconds |
| Started | Aug 04 04:31:21 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 206996 kb |
| Host | smart-15819528-90ec-43cd-9347-0db20354537e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=814541621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.814541621 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2634558799 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 38091408 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:31:40 PM PDT 24 |
| Finished | Aug 04 04:31:40 PM PDT 24 |
| Peak memory | 206708 kb |
| Host | smart-84a00b16-bfe0-4a0e-90f8-38eed5a20735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2634558799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2634558799 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.2947169022 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 155787099 ps |
| CPU time | 1.57 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 206996 kb |
| Host | smart-c904b34b-80fd-4d76-9fd6-6d16d05e8c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2947169022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.2947169022 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3400642852 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 100496846 ps |
| CPU time | 2.6 seconds |
| Started | Aug 04 04:31:36 PM PDT 24 |
| Finished | Aug 04 04:31:38 PM PDT 24 |
| Peak memory | 223244 kb |
| Host | smart-bf3c70ce-bbf2-4027-b133-bf7588a15e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3400642852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3400642852 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1143707500 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 570641689 ps |
| CPU time | 2.77 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:45 PM PDT 24 |
| Peak memory | 207056 kb |
| Host | smart-80fb9855-010e-4e11-9f3a-9cb4aaf52742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1143707500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1143707500 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.388655193 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 156734563 ps |
| CPU time | 1.83 seconds |
| Started | Aug 04 04:31:34 PM PDT 24 |
| Finished | Aug 04 04:31:36 PM PDT 24 |
| Peak memory | 215284 kb |
| Host | smart-1946b817-2982-492c-bc72-c141b8c5a947 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388655193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev _csr_mem_rw_with_rand_reset.388655193 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1444970276 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 73245330 ps |
| CPU time | 0.94 seconds |
| Started | Aug 04 04:32:37 PM PDT 24 |
| Finished | Aug 04 04:32:38 PM PDT 24 |
| Peak memory | 206844 kb |
| Host | smart-a649b60c-344b-4e3e-9e65-2755bb7b6d95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1444970276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1444970276 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1795047323 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 64332901 ps |
| CPU time | 0.71 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:31 PM PDT 24 |
| Peak memory | 206676 kb |
| Host | smart-69eeb950-6e14-467a-b275-9f4dbad1f678 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1795047323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1795047323 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4159174586 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 184076926 ps |
| CPU time | 1.58 seconds |
| Started | Aug 04 04:31:19 PM PDT 24 |
| Finished | Aug 04 04:31:22 PM PDT 24 |
| Peak memory | 207032 kb |
| Host | smart-1025d50c-f282-483d-a201-f272528cdb20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4159174586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4159174586 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.985649502 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 240763862 ps |
| CPU time | 2.18 seconds |
| Started | Aug 04 04:31:35 PM PDT 24 |
| Finished | Aug 04 04:31:37 PM PDT 24 |
| Peak memory | 207076 kb |
| Host | smart-dcca43f6-14cf-4720-a206-7854d0c3bb05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=985649502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.985649502 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.759637279 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 469933453 ps |
| CPU time | 2.49 seconds |
| Started | Aug 04 04:32:55 PM PDT 24 |
| Finished | Aug 04 04:32:58 PM PDT 24 |
| Peak memory | 207024 kb |
| Host | smart-a349f6a7-8fbb-4049-bb46-8c5a520690d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=759637279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.759637279 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.938098958 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 83469952 ps |
| CPU time | 1.13 seconds |
| Started | Aug 04 04:31:20 PM PDT 24 |
| Finished | Aug 04 04:31:21 PM PDT 24 |
| Peak memory | 215056 kb |
| Host | smart-95b1bf80-78e5-43d9-9c0e-465938858f6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938098958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev _csr_mem_rw_with_rand_reset.938098958 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4205048585 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 169993623 ps |
| CPU time | 0.95 seconds |
| Started | Aug 04 04:31:24 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 206912 kb |
| Host | smart-b3481b40-0ce4-4a13-943e-ce91ffae735e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4205048585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4205048585 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.168693389 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 42790005 ps |
| CPU time | 0.76 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 206676 kb |
| Host | smart-24b560db-30a0-4e84-884b-d828cd3f5945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=168693389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.168693389 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.154975314 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 143318584 ps |
| CPU time | 1.23 seconds |
| Started | Aug 04 04:31:31 PM PDT 24 |
| Finished | Aug 04 04:31:32 PM PDT 24 |
| Peak memory | 207092 kb |
| Host | smart-cbc5c096-3941-420b-94a6-98dbe1223459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=154975314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.154975314 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3076279981 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 78919087 ps |
| CPU time | 1.39 seconds |
| Started | Aug 04 04:31:28 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 207052 kb |
| Host | smart-4e6d0f9d-3820-4205-b328-92a421c8a42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3076279981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3076279981 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.915277558 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 490074316 ps |
| CPU time | 2.35 seconds |
| Started | Aug 04 04:32:33 PM PDT 24 |
| Finished | Aug 04 04:32:35 PM PDT 24 |
| Peak memory | 207020 kb |
| Host | smart-59899d4a-e35e-474d-b5ed-a6f2bbe6a70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=915277558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.915277558 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.958767202 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 109979946 ps |
| CPU time | 2.9 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:25 PM PDT 24 |
| Peak memory | 215320 kb |
| Host | smart-415d223d-915e-4f52-9304-2ce08ae89f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958767202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev _csr_mem_rw_with_rand_reset.958767202 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2618239918 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 68987075 ps |
| CPU time | 0.8 seconds |
| Started | Aug 04 04:31:30 PM PDT 24 |
| Finished | Aug 04 04:31:31 PM PDT 24 |
| Peak memory | 206920 kb |
| Host | smart-b371a6c1-e2c7-4849-b5aa-e79654093070 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2618239918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2618239918 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1109081421 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 41724992 ps |
| CPU time | 0.72 seconds |
| Started | Aug 04 04:31:28 PM PDT 24 |
| Finished | Aug 04 04:31:29 PM PDT 24 |
| Peak memory | 206676 kb |
| Host | smart-098f69b6-98e4-416e-8bff-0cefb2e72dd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1109081421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1109081421 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3383662686 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 134815689 ps |
| CPU time | 1.25 seconds |
| Started | Aug 04 04:31:38 PM PDT 24 |
| Finished | Aug 04 04:31:39 PM PDT 24 |
| Peak memory | 207072 kb |
| Host | smart-9bcbaa86-2995-438b-bda4-2be62b3db8cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3383662686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3383662686 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.4092752205 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 254283778 ps |
| CPU time | 3.18 seconds |
| Started | Aug 04 04:31:37 PM PDT 24 |
| Finished | Aug 04 04:31:41 PM PDT 24 |
| Peak memory | 207100 kb |
| Host | smart-f5fd0e7d-669d-49e4-9595-cccd4bc9172d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4092752205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.4092752205 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.2616396622 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 826882792 ps |
| CPU time | 5.2 seconds |
| Started | Aug 04 04:31:27 PM PDT 24 |
| Finished | Aug 04 04:31:32 PM PDT 24 |
| Peak memory | 207064 kb |
| Host | smart-09da567c-b0e3-4237-a1a1-1843e6d2a49a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2616396622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.2616396622 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2022224635 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 69826402 ps |
| CPU time | 1.62 seconds |
| Started | Aug 04 04:31:41 PM PDT 24 |
| Finished | Aug 04 04:31:43 PM PDT 24 |
| Peak memory | 219664 kb |
| Host | smart-32ad9462-76ce-4cbc-8cd2-1e5785ef8b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022224635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.2022224635 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2841217885 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 102542258 ps |
| CPU time | 1.05 seconds |
| Started | Aug 04 04:31:47 PM PDT 24 |
| Finished | Aug 04 04:31:48 PM PDT 24 |
| Peak memory | 206924 kb |
| Host | smart-6b3bb094-b278-418c-9d65-6a26349adae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2841217885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2841217885 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3598733248 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 47645416 ps |
| CPU time | 0.69 seconds |
| Started | Aug 04 04:31:22 PM PDT 24 |
| Finished | Aug 04 04:31:23 PM PDT 24 |
| Peak memory | 206784 kb |
| Host | smart-a787476d-e96c-41fe-895b-ca468c28e12f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3598733248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3598733248 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3496833962 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 265507414 ps |
| CPU time | 1.76 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:27 PM PDT 24 |
| Peak memory | 207088 kb |
| Host | smart-812dcc6d-0a3f-4f51-8191-71c83a72b14a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3496833962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3496833962 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2899883843 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 133345235 ps |
| CPU time | 1.72 seconds |
| Started | Aug 04 04:31:19 PM PDT 24 |
| Finished | Aug 04 04:31:21 PM PDT 24 |
| Peak memory | 207140 kb |
| Host | smart-49ceaf15-3fce-4449-8001-9a63d57ed43f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2899883843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2899883843 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2793896644 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 832584064 ps |
| CPU time | 5.08 seconds |
| Started | Aug 04 04:31:25 PM PDT 24 |
| Finished | Aug 04 04:31:30 PM PDT 24 |
| Peak memory | 207172 kb |
| Host | smart-5a2b4434-a07f-46bc-b181-6241c21a5825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2793896644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2793896644 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |