Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	344	1		T6	2		T16	5		T12	5
all_pins[1]	344	1		T6	2		T16	5		T12	5
all_pins[2]	344	1		T6	2		T16	5		T12	5
all_pins[3]	344	1		T6	2		T16	5		T12	5
all_pins[4]	344	1		T6	2		T16	5		T12	5
all_pins[5]	344	1		T6	2		T16	5		T12	5
all_pins[6]	344	1		T6	2		T16	5		T12	5
all_pins[7]	344	1		T6	2		T16	5		T12	5
all_pins[8]	344	1		T6	2		T16	5		T12	5
all_pins[9]	344	1		T6	2		T16	5		T12	5
all_pins[10]	344	1		T6	2		T16	5		T12	5
all_pins[11]	344	1		T6	2		T16	5		T12	5
all_pins[12]	344	1		T6	2		T16	5		T12	5
all_pins[13]	344	1		T6	2		T16	5		T12	5
all_pins[14]	344	1		T6	2		T16	5		T12	5
all_pins[15]	344	1		T6	2		T16	5		T12	5
all_pins[16]	344	1		T6	2		T16	5		T12	5
all_pins[17]	344	1		T6	2		T16	5		T12	5

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	9968	1		T6	64		T16	143		T12	139
values[0x1]	1040	1		T16	17		T12	21		T13	27
transitions[0x0=>0x1]	822	1		T16	13		T12	15		T13	26
transitions[0x1=>0x0]	822	1		T16	13		T12	15		T13	26

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	288	1		T6	2		T16	5		T12	4
all_pins[0]	values[0x1]	56	1		T12	1		T13	1		T14	2
all_pins[0]	transitions[0x0=>0x1]	39	1		T12	1		T13	1		T14	2
all_pins[0]	transitions[0x1=>0x0]	32	1		T12	1		T13	2		T59	1
all_pins[1]	values[0x0]	295	1		T6	2		T16	5		T12	4
all_pins[1]	values[0x1]	49	1		T12	1		T13	2		T15	1
all_pins[1]	transitions[0x0=>0x1]	38	1		T13	2		T15	1		T59	2
all_pins[1]	transitions[0x1=>0x0]	57	1		T13	1		T59	2		T61	5
all_pins[2]	values[0x0]	276	1		T6	2		T16	5		T12	4
all_pins[2]	values[0x1]	68	1		T12	1		T13	1		T59	2
all_pins[2]	transitions[0x0=>0x1]	48	1		T12	1		T13	1		T59	2
all_pins[2]	transitions[0x1=>0x0]	53	1		T16	2		T12	3		T59	1
all_pins[3]	values[0x0]	271	1		T6	2		T16	3		T12	2
all_pins[3]	values[0x1]	73	1		T16	2		T12	3		T59	1
all_pins[3]	transitions[0x0=>0x1]	55	1		T12	2		T59	1		T61	3
all_pins[3]	transitions[0x1=>0x0]	46	1		T16	2		T13	3		T15	2
all_pins[4]	values[0x0]	280	1		T6	2		T16	1		T12	4
all_pins[4]	values[0x1]	64	1		T16	4		T12	1		T13	3
all_pins[4]	transitions[0x0=>0x1]	48	1		T16	4		T13	3		T15	2
all_pins[4]	transitions[0x1=>0x0]	44	1		T12	3		T13	1		T14	3
all_pins[5]	values[0x0]	284	1		T6	2		T16	5		T12	1
all_pins[5]	values[0x1]	60	1		T12	4		T13	1		T14	3
all_pins[5]	transitions[0x0=>0x1]	49	1		T12	4		T14	3		T59	3
all_pins[5]	transitions[0x1=>0x0]	60	1		T13	2		T15	2		T61	1
all_pins[6]	values[0x0]	273	1		T6	2		T16	5		T12	5
all_pins[6]	values[0x1]	71	1		T13	3		T15	2		T61	1
all_pins[6]	transitions[0x0=>0x1]	63	1		T13	3		T15	2		T61	1
all_pins[6]	transitions[0x1=>0x0]	40	1		T16	1		T12	2		T13	1
all_pins[7]	values[0x0]	296	1		T6	2		T16	4		T12	3
all_pins[7]	values[0x1]	48	1		T16	1		T12	2		T13	1
all_pins[7]	transitions[0x0=>0x1]	34	1		T12	1		T13	1		T14	1
all_pins[7]	transitions[0x1=>0x0]	39	1		T16	1		T12	1		T13	1
all_pins[8]	values[0x0]	291	1		T6	2		T16	3		T12	3
all_pins[8]	values[0x1]	53	1		T16	2		T12	2		T13	1
all_pins[8]	transitions[0x0=>0x1]	39	1		T16	1		T13	1		T15	1
all_pins[8]	transitions[0x1=>0x0]	53	1		T16	1		T13	2		T14	2
all_pins[9]	values[0x0]	277	1		T6	2		T16	3		T12	3
all_pins[9]	values[0x1]	67	1		T16	2		T12	2		T13	2
all_pins[9]	transitions[0x0=>0x1]	52	1		T16	2		T12	2		T13	2
all_pins[9]	transitions[0x1=>0x0]	34	1		T13	1		T59	1		T61	2
all_pins[10]	values[0x0]	295	1		T6	2		T16	5		T12	5
all_pins[10]	values[0x1]	49	1		T13	1		T14	3		T59	1
all_pins[10]	transitions[0x0=>0x1]	40	1		T13	1		T14	3		T61	3
all_pins[10]	transitions[0x1=>0x0]	52	1		T13	1		T15	3		T61	1
all_pins[11]	values[0x0]	283	1		T6	2		T16	5		T12	5
all_pins[11]	values[0x1]	61	1		T13	1		T15	3		T59	1
all_pins[11]	transitions[0x0=>0x1]	44	1		T13	1		T15	1		T61	1
all_pins[11]	transitions[0x1=>0x0]	33	1		T12	1		T14	3		T59	2
all_pins[12]	values[0x0]	294	1		T6	2		T16	5		T12	4
all_pins[12]	values[0x1]	50	1		T12	1		T14	3		T15	2
all_pins[12]	transitions[0x0=>0x1]	40	1		T12	1		T14	3		T59	3
all_pins[12]	transitions[0x1=>0x0]	42	1		T16	3		T13	1		T15	1
all_pins[13]	values[0x0]	292	1		T6	2		T16	2		T12	5
all_pins[13]	values[0x1]	52	1		T16	3		T13	1		T15	3
all_pins[13]	transitions[0x0=>0x1]	42	1		T16	3		T13	1		T15	3
all_pins[13]	transitions[0x1=>0x0]	44	1		T13	5		T14	2		T59	1
all_pins[14]	values[0x0]	290	1		T6	2		T16	5		T12	5
all_pins[14]	values[0x1]	54	1		T13	5		T14	2		T59	1
all_pins[14]	transitions[0x0=>0x1]	49	1		T13	5		T14	2		T59	1
all_pins[14]	transitions[0x1=>0x0]	38	1		T16	2		T12	2		T61	3
all_pins[15]	values[0x0]	301	1		T6	2		T16	3		T12	3
all_pins[15]	values[0x1]	43	1		T16	2		T12	2		T61	3
all_pins[15]	transitions[0x0=>0x1]	35	1		T16	2		T12	2		T61	1
all_pins[15]	transitions[0x1=>0x0]	50	1		T13	3		T14	2		T15	2
all_pins[16]	values[0x0]	286	1		T6	2		T16	5		T12	5
all_pins[16]	values[0x1]	58	1		T13	3		T14	2		T15	2
all_pins[16]	transitions[0x0=>0x1]	43	1		T13	3		T14	1		T15	2
all_pins[16]	transitions[0x1=>0x0]	49	1		T16	1		T12	1		T13	1
all_pins[17]	values[0x0]	280	1		T6	2		T16	4		T12	4
all_pins[17]	values[0x1]	64	1		T16	1		T12	1		T13	1
all_pins[17]	transitions[0x0=>0x1]	64	1		T16	1		T12	1		T13	1